[llvm] c1bb2d0 - [RISCV] Common post-mask operand construction in performCombineVMergeAndVOps [nfc]

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2023-07-13T10:39:52-07:00
New Revision: c1bb2d0b6c1acc31a6abbd669ecb6554b3a9797e

URL: https://github.com/llvm/llvm-project/commit/c1bb2d0b6c1acc31a6abbd669ecb6554b3a9797e
DIFF: https://github.com/llvm/llvm-project/commit/c1bb2d0b6c1acc31a6abbd669ecb6554b3a9797e.diff

LOG: [RISCV] Common post-mask operand construction in performCombineVMergeAndVOps [nfc]

This is a subset of Luke's D155063.  I'm splitting pieces and landing them in the process of convincing myself all the individual transforms are in fact correct.

This particular change involves a slightly ugly bit of code to match the glue to the mask.  I'm staging it this way as I ran into a bit of weirdness when commoning mask operands, and wanted to isolate the complexity.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 8b29524072ded4..36bfe3d46a1bf3 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -3341,8 +3341,6 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N) {
   if (IsMasked) {
     Ops.push_back(False);
     Ops.append(True->op_begin() + 1, True->op_begin() + TrueVLIndex);
-    Ops.append({VL, SEW, PolicyOp});
-    Ops.append(True->op_begin() + TrueVLIndex + 3, True->op_end());
   } else {
     Ops.push_back(False);
     if (RISCVII::hasRoundModeOp(TrueTSFlags)) {
@@ -3359,15 +3357,20 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N) {
                  True->op_begin() + TrueVLIndex);
       Ops.push_back(Mask);
     }
-    Ops.append({VL, SEW, PolicyOp});
+  }
+  Ops.append({VL, SEW, PolicyOp});
 
-    // Result node should have chain operand of True.
-    if (HasChainOp)
-      Ops.push_back(True.getOperand(TrueChainOpIdx));
+  // Result node should have chain operand of True.
+  if (HasChainOp)
+    Ops.push_back(True.getOperand(TrueChainOpIdx));
 
-    // Add the glue for the CopyToReg of mask->v0.
-    Ops.push_back(Glue);
+  // Add the glue for the CopyToReg of mask->v0.
+  if (IsMasked) {
+    // Matches the Merge operand above
+    assert(True->getGluedNode());
+    Glue = True->getOperand(True->getNumOperands() - 1);
   }
+  Ops.push_back(Glue);
 
   SDNode *Result =
       CurDAG->getMachineNode(MaskedOpc, DL, True->getVTList(), Ops);