[llvm] f648c9f - [RISCV] Tail common repeated code in performCombineVMergeAndVOps [nfc]

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2023-07-13T10:07:09-07:00
New Revision: f648c9f71ee0cb619eac82b2bf5b5ca94c702555

URL: https://github.com/llvm/llvm-project/commit/f648c9f71ee0cb619eac82b2bf5b5ca94c702555
DIFF: https://github.com/llvm/llvm-project/commit/f648c9f71ee0cb619eac82b2bf5b5ca94c702555.diff

LOG: [RISCV] Tail common repeated code in performCombineVMergeAndVOps [nfc]

Very minor change, just making sure each step is obvious and easy to follow.

This is a subset of Luke's D155063.  I'm splitting pieces and landing them in the process of convincing myself all the individual transforms are in fact correct.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 1710f958b73a46..8b29524072ded4 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -3353,13 +3353,13 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N) {
       SDValue RoundMode = True->getOperand(TrueVLIndex - 1);
       Ops.append(True->op_begin() + HasTiedDest,
                  True->op_begin() + TrueVLIndex - 1);
-      Ops.append({Mask, RoundMode, VL, SEW});
+      Ops.append({Mask, RoundMode});
     } else {
       Ops.append(True->op_begin() + HasTiedDest,
                  True->op_begin() + TrueVLIndex);
-      Ops.append({Mask, VL, SEW});
+      Ops.push_back(Mask);
     }
-    Ops.push_back(PolicyOp);
+    Ops.append({VL, SEW, PolicyOp});
 
     // Result node should have chain operand of True.
     if (HasChainOp)