[llvm] ca8ef82 - [RISCV] Factor out a dupiicate bit of repeated code in performCombineVMergeAndVOps [nfc]

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2023-07-13T09:59:02-07:00
New Revision: ca8ef82165dc169e79bced70ae46f614aa456811

URL: https://github.com/llvm/llvm-project/commit/ca8ef82165dc169e79bced70ae46f614aa456811
DIFF: https://github.com/llvm/llvm-project/commit/ca8ef82165dc169e79bced70ae46f614aa456811.diff

LOG: [RISCV] Factor out a dupiicate bit of repeated code in performCombineVMergeAndVOps [nfc]

We have the SEW operand access repeating in all paths, common it up to make the code easier to read.

This is a subset of Luke's D155063.  I'm splitting pieces and landing them in the process of convincing myself all the individual transforms are in fact correct.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index e8e22352670ffc..1710f958b73a46 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -3329,17 +3329,19 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N) {
          "Expected instructions with mask have a tied dest.");
 #endif
 
+  SDValue SEW = True.getOperand(TrueVLIndex + 1);
+
   uint64_t Policy = isImplicitDef(N->getOperand(0)) ?
     RISCVII::TAIL_AGNOSTIC : /*TUMU*/ 0;
   SDValue PolicyOp =
     CurDAG->getTargetConstant(Policy, DL, Subtarget->getXLenVT());
 
+
   SmallVector<SDValue, 8> Ops;
   if (IsMasked) {
     Ops.push_back(False);
     Ops.append(True->op_begin() + 1, True->op_begin() + TrueVLIndex);
-    Ops.append({VL, /* SEW */ True.getOperand(TrueVLIndex + 1)});
-    Ops.push_back(PolicyOp);
+    Ops.append({VL, SEW, PolicyOp});
     Ops.append(True->op_begin() + TrueVLIndex + 3, True->op_end());
   } else {
     Ops.push_back(False);
@@ -3351,12 +3353,11 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N) {
       SDValue RoundMode = True->getOperand(TrueVLIndex - 1);
       Ops.append(True->op_begin() + HasTiedDest,
                  True->op_begin() + TrueVLIndex - 1);
-      Ops.append(
-          {Mask, RoundMode, VL, /* SEW */ True.getOperand(TrueVLIndex + 1)});
+      Ops.append({Mask, RoundMode, VL, SEW});
     } else {
       Ops.append(True->op_begin() + HasTiedDest,
                  True->op_begin() + TrueVLIndex);
-      Ops.append({Mask, VL, /* SEW */ True.getOperand(TrueVLIndex + 1)});
+      Ops.append({Mask, VL, SEW});
     }
     Ops.push_back(PolicyOp);