[llvm] f4ba1db - [GlobalISel] Fix the error transformation of BRCOND to BCC

[via llvm-commits]

Author: hezuoqiang
Date: 2023-07-13T21:20:01+08:00
New Revision: f4ba1db5bf88e5f8fc5348e20c02df66e865cdb1

URL: https://github.com/llvm/llvm-project/commit/f4ba1db5bf88e5f8fc5348e20c02df66e865cdb1
DIFF: https://github.com/llvm/llvm-project/commit/f4ba1db5bf88e5f8fc5348e20c02df66e865cdb1.diff

LOG: [GlobalISel] Fix the error transformation of BRCOND to BCC

Fix https://github.com/llvm/llvm-project/issues/62309

Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D150527

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
    llvm/test/CodeGen/AArch64/GlobalISel/speculative-hardening-brcond.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index eb2e4172e0235d..b8af6a2be46837 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -1785,7 +1785,7 @@ bool AArch64InstructionSelector::selectCompareBranch(
       MIB.buildInstr(AArch64::ANDSWri, {LLT::scalar(32)}, {CondReg}).addImm(1);
   constrainSelectedInstRegOperands(*TstMI, TII, TRI, RBI);
   auto Bcc = MIB.buildInstr(AArch64::Bcc)
-                 .addImm(AArch64CC::EQ)
+                 .addImm(AArch64CC::NE)
                  .addMBB(I.getOperand(1).getMBB());
   I.eraseFromParent();
   return constrainSelectedInstRegOperands(*Bcc, TII, TRI, RBI);

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/speculative-hardening-brcond.mir b/llvm/test/CodeGen/AArch64/GlobalISel/speculative-hardening-brcond.mir
index 3f5045f3cb8996..a158f2466dce7d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/speculative-hardening-brcond.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/speculative-hardening-brcond.mir
@@ -21,7 +21,7 @@ body:             |
   ; CHECK:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
   ; CHECK:   %reg:gpr32 = COPY $w0
   ; CHECK:   [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg, 1, implicit-def $nzcv
-  ; CHECK:   Bcc 0, %bb.1, implicit $nzcv
+  ; CHECK:   Bcc 1, %bb.1, implicit $nzcv
   ; CHECK:   B %bb.0
   ; CHECK: bb.1:
   ; CHECK:   RET_ReallyLR