[PATCH] D154445: [Mips] Fix argument lowering for illegal vector types (PR63608)

[Nikita Popov via Phabricator via llvm-commits]

nikic added a comment.

In D154445#4478797 <https://reviews.llvm.org/D154445#4478797>, @arsenm wrote:

>> However, the SDAG argument lowering code doesn't support this,
>
> How? I thought that was working reasonably OK these days

MIPS uses an unusual calling convention where vectors (even legal vectors) get passed in GPR registers in packed representation (i.e. multiple vector elements per GPR register). Outside of MIPS, we should usually either pass in legalized vector registers, or element-wise in GPR registers.

I initially wanted to support non-pow2 vectors that follow the usual MIPS vector ABI and implemented this in https://gist.github.com/nikic/a52f764ee0ba211ddfd98a50e3df009d. This basically adds support for combination of bitcast and widening/narrowing. The problem is that when we get to non-pow2 element sizes, this becomes a lot less straightforward. E.g. v7i18 needs to be passed as two i64 registers, but `v7i18` and `v2i64` don't even have the same size, so we can't bitcast between them. We'd have to do something like bitcast `v2i64` to `i128` first, then truncate to `i126`, then bitcast to `v7i18`. It doesn't seem worthwhile to me to add this complexity to SDAG lowering, if we don't have to match any particular ABI for the non-pow2 cases.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154445/new/

https://reviews.llvm.org/D154445