[PATCH] D154635: [7/8][RISCV] Add rounding mode control variant for conversion intrinsics between floating-point and integer

[Yueh-Ting (eop) Chen via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG5d18d43f26ad: [7/8][RISCV] Add rounding mode control variant for conversion intrinsics… (authored by eopXD).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154635/new/

https://reviews.llvm.org/D154635

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfcvt-out-of-range.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfncvt-out-of-range.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfwcvt-out-of-range.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
  llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll