[llvm] 40779e8 - [RISCV] Correct even register check for amocas.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-07-12T12:58:01-07:00
New Revision: 40779e840062eafcfee7b16e28bc600ebf12ac3a

URL: https://github.com/llvm/llvm-project/commit/40779e840062eafcfee7b16e28bc600ebf12ac3a
DIFF: https://github.com/llvm/llvm-project/commit/40779e840062eafcfee7b16e28bc600ebf12ac3a.diff

LOG: [RISCV] Correct even register check for amocas.

We were checking that the encoding within our internal list of
registers was even. This worked today because X0 happens to have
an even value in that enum. This can break if any registers are
added before X0.

The correct check is to make sure it has an even offset from X0.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D155104

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index dc1ce01d958f96..b53498097b855f 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -3285,11 +3285,13 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst,
   if ((!isRV64() && IsAMOCAS_D) || IsAMOCAS_Q) {
     unsigned Rd = Inst.getOperand(0).getReg();
     unsigned Rs2 = Inst.getOperand(2).getReg();
-    if (Rd % 2 != 0) {
+    assert(Rd >= RISCV::X0 && Rd <= RISCV::X31);
+    if ((Rd - RISCV::X0) % 2 != 0) {
       SMLoc Loc = Operands[1]->getStartLoc();
       return Error(Loc, "The destination register must be even.");
     }
-    if (Rs2 % 2 != 0) {
+    assert(Rs2 >= RISCV::X0 && Rs2 <= RISCV::X31);
+    if ((Rs2 - RISCV::X0) % 2 != 0) {
       SMLoc Loc = Operands[2]->getStartLoc();
       return Error(Loc, "The source register must be even.");
     }