[PATCH] D153974: [RISCV] Don't include X1 in the X0_PD register pair

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D153974#4494029 <https://reviews.llvm.org/D153974#4494029>, @asb wrote:

> In D153974#4493649 <https://reviews.llvm.org/D153974#4493649>, @craig.topper wrote:
>
>> Do we need to reserve the new register in `RISCVRegisterInfo::getReservedRegs`?
>
> Good suggestion. We might need to, but unfortunately that has no impact on the changed test case.

Marking the register reserved and adding this to RISCVRegisterInfo.td recovers the tests.

  def GPRAll : GPRRegisterClass<(add GPR, DUMMY_REG_PAIR_WITH_X0)>;


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https://reviews.llvm.org/D153974