[PATCH] D154447: [PowerPC] Improve code gen for vector add

[Lei Huang via Phabricator via llvm-commits]

lei updated this revision to Diff 539655.
lei added a comment.

add new tc and update to test for pwr8 since we are more interested
in the new tc behaviour for pwr8 and orig tc is same for pwr8 vs pwr7.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154447/new/

https://reviews.llvm.org/D154447

Files:
  llvm/lib/Target/PowerPC/PPCInstrAltivec.td
  llvm/test/CodeGen/PowerPC/optimize-vector.ll


Index: llvm/test/CodeGen/PowerPC/optimize-vector.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/optimize-vector.ll
+++ llvm/test/CodeGen/PowerPC/optimize-vector.ll
@@ -1,13 +1,12 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
-; RUN:   -mcpu=pwr7 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
 ; RUN:   FileCheck %s
 
 define dso_local <16 x i8> @x2(<16 x i8> noundef %x) {
 ; CHECK-LABEL: x2:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vspltisb v3, 1
-; CHECK-NEXT:    vslb v2, v2, v3
+; CHECK-NEXT:    vaddubm v2, v2, v2
 ; CHECK-NEXT:    blr
 entry:
   %add = shl <16 x i8> %x, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
@@ -17,8 +16,7 @@
 define dso_local <8 x i16> @x2h(<8 x i16> noundef %x) {
 ; CHECK-LABEL: x2h:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vspltish v3, 1
-; CHECK-NEXT:    vslh v2, v2, v3
+; CHECK-NEXT:    vadduhm v2, v2, v2
 ; CHECK-NEXT:    blr
 entry:
   %add = shl <8 x i16> %x, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
@@ -28,10 +26,22 @@
 define dso_local <4 x i32> @x2w(<4 x i32> noundef %x) {
 ; CHECK-LABEL: x2w:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vspltisw v3, 1
-; CHECK-NEXT:    vslw v2, v2, v3
+; CHECK-NEXT:    vadduwm v2, v2, v2
 ; CHECK-NEXT:    blr
 entry:
   %add = shl <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1>
   ret <4 x i32> %add
 }
+
+define dso_local <2 x i64> @x2d(<2 x i64> noundef %x) {
+; CHECK-LABEL: x2d:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r3, r2, .LCPI3_0 at toc@ha
+; CHECK-NEXT:    addi r3, r3, .LCPI3_0 at toc@l
+; CHECK-NEXT:    lxvd2x v3, 0, r3
+; CHECK-NEXT:    vsld v2, v2, v3
+; CHECK-NEXT:    blr
+entry:
+  %add = shl <2 x i64> %x, <i64 1, i64 1>
+  ret <2 x i64> %add
+}
Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td
@@ -1161,6 +1161,13 @@
 def : Pat<(v16i8 (srl (sub v16i8:$vA, (v16i8 (bitconvert(vnot v4i32:$vB)))),
           (v16i8 (immEQOneV)))), (v16i8 (VAVGUB $vA, $vB))>;
 
+def : Pat<(v16i8 (shl v16i8:$vA, (v16i8 (immEQOneV)))),
+          (v16i8 (VADDUBM $vA, $vA))>;
+def : Pat<(v8i16 (shl v8i16:$vA, (v8i16 (immEQOneV)))),
+          (v8i16 (VADDUHM $vA, $vA))>;
+def : Pat<(v4i32 (shl v4i32:$vA, (v4i32 (immEQOneV)))),
+          (v4i32 (VADDUWM $vA, $vA))>;
+
 } // end HasAltivec
 
 // [PO VRT VRA VRB 1 PS XO], "_o" means CR6 is set.


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