[llvm] 6c388e0 - [LSR] Convert test to opaque pointers (NFC)

[Nikita Popov via llvm-commits]

Author: Nikita Popov
Date: 2023-07-12T14:07:25+02:00
New Revision: 6c388e06f5f32c19ee0e7e45198eb7a2b48c5f3d

URL: https://github.com/llvm/llvm-project/commit/6c388e06f5f32c19ee0e7e45198eb7a2b48c5f3d
DIFF: https://github.com/llvm/llvm-project/commit/6c388e06f5f32c19ee0e7e45198eb7a2b48c5f3d.diff

LOG: [LSR] Convert test to opaque pointers (NFC)

This regresses with opaque pointers. I'll submit a patch to recover
the regression.

Added: 
    

Modified: 
    llvm/test/Transforms/LoopStrengthReduce/AArch64/lsr-memcpy.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/LoopStrengthReduce/AArch64/lsr-memcpy.ll b/llvm/test/Transforms/LoopStrengthReduce/AArch64/lsr-memcpy.ll
index a4b59a9f48495a..c2d15a3870bf65 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/AArch64/lsr-memcpy.ll
+++ b/llvm/test/Transforms/LoopStrengthReduce/AArch64/lsr-memcpy.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -opaque-pointers=0 -mtriple=arm64-unknown-unknown -mcpu=cyclone -pre-RA-sched=list-hybrid < %s | FileCheck %s
+; RUN: llc -mtriple=arm64-unknown-unknown -mcpu=cyclone -pre-RA-sched=list-hybrid < %s | FileCheck %s
 ; rdar://10232252
 ; Prevent LSR of doing poor choice that cannot be folded in addressing mode
 
@@ -7,18 +7,21 @@
 ; <rdar://problem/12702735> [ARM64][coalescer] need better register
 ; coalescing for simple unit tests.
 
+; FIXME: This regressed after enabling opaque pointers.
 define i32 @testCase() nounwind ssp {
 ; CHECK-LABEL: testCase:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT:    mov w8, #1288 // =0x508
-; CHECK-NEXT:    mov x9, #4294967296 // =0x100000000
-; CHECK-NEXT:    mov x10, #6442450944 // =0x180000000
+; CHECK-NEXT:    mov x8, #0 // =0x0
+; CHECK-NEXT:    mov w9, #1288 // =0x508
+; CHECK-NEXT:    mov x10, #4294967296 // =0x100000000
+; CHECK-NEXT:    mov x11, #6442450944 // =0x180000000
 ; CHECK-NEXT:  .LBB0_1: // %while.body
 ; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    ldr x11, [x9], #8
-; CHECK-NEXT:    str x11, [x10], #8
-; CHECK-NEXT:    subs x8, x8, #8
+; CHECK-NEXT:    ldr x12, [x8, x10]
+; CHECK-NEXT:    str x12, [x8, x11]
+; CHECK-NEXT:    add x8, x8, #8
+; CHECK-NEXT:    subs x9, x9, #8
 ; CHECK-NEXT:    b.pl .LBB0_1
 ; CHECK-NEXT:  // %bb.2: // %while.end
 ; CHECK-NEXT:    mov x8, #6442450944 // =0x180000000
@@ -31,17 +34,17 @@ entry:
 
 while.body:                                       ; preds = %while.body, %entry
   %len.06 = phi i64 [ 1288, %entry ], [ %sub, %while.body ]
-  %pDst.05 = phi i64* [ inttoptr (i64 6442450944 to i64*), %entry ], [ %incdec.ptr1, %while.body ]
-  %pSrc.04 = phi i64* [ inttoptr (i64 4294967296 to i64*), %entry ], [ %incdec.ptr, %while.body ]
-  %incdec.ptr = getelementptr inbounds i64, i64* %pSrc.04, i64 1
-  %tmp = load volatile i64, i64* %pSrc.04, align 8
-  %incdec.ptr1 = getelementptr inbounds i64, i64* %pDst.05, i64 1
-  store volatile i64 %tmp, i64* %pDst.05, align 8
+  %pDst.05 = phi ptr [ inttoptr (i64 6442450944 to ptr), %entry ], [ %incdec.ptr1, %while.body ]
+  %pSrc.04 = phi ptr [ inttoptr (i64 4294967296 to ptr), %entry ], [ %incdec.ptr, %while.body ]
+  %incdec.ptr = getelementptr inbounds i64, ptr %pSrc.04, i64 1
+  %tmp = load volatile i64, ptr %pSrc.04, align 8
+  %incdec.ptr1 = getelementptr inbounds i64, ptr %pDst.05, i64 1
+  store volatile i64 %tmp, ptr %pDst.05, align 8
   %sub = add i64 %len.06, -8
   %cmp = icmp sgt i64 %sub, -1
   br i1 %cmp, label %while.body, label %while.end
 
 while.end:                                        ; preds = %while.body
-  tail call void inttoptr (i64 6442450944 to void ()*)() nounwind
+  tail call void inttoptr (i64 6442450944 to ptr)() nounwind
   ret i32 0
 }