[PATCH] D155055: [WIP][AMDGPU] Divergence-driven instruction selection for fshr

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/bf16.ll:631
 ; GCN-NEXT:    s_mov_b32 s6, 0
-; GCN-NEXT:    v_alignbit_b32 v0, v1, v0, 16
+; GCN-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GCN-NEXT:    s_mov_b32 s7, 0xf000
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There are lots of minor regressions like this. I will investigate.


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Comment at: llvm/test/CodeGen/AMDGPU/build_vector.ll:74
 ; GFX6: s_waitcnt lgkmcnt(0)
-; GFX6: v_alignbit_b32 v0, 5, s4, 16
+; GFX6: s_lshr_b32 s2, s2, 16
+; GFX6: s_or_b32 s4, s2, 0x50000
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This is the intended change. In general we should select SALU instructions for uniform calculations, even if it's more instructions. In this case it's a shame that the result gets copied to a VGPR anyway...


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155055/new/

https://reviews.llvm.org/D155055