[llvm] d69033d - [SCEVExpander] Fix GEP IV inc reuse logic for opaque pointers
Nikita Popov via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 12 02:32:22 PDT 2023
Author: Nikita Popov
Date: 2023-07-12T11:32:13+02:00
New Revision: d69033d245d4e129142b3908b8d406cdd897c9c9
URL: https://github.com/llvm/llvm-project/commit/d69033d245d4e129142b3908b8d406cdd897c9c9
DIFF: https://github.com/llvm/llvm-project/commit/d69033d245d4e129142b3908b8d406cdd897c9c9.diff
LOG: [SCEVExpander] Fix GEP IV inc reuse logic for opaque pointers
Instead of checking the pointer type, check the element type of
the GEP.
Previously we ended up reusing GEP increments that were not in
expanded form, thus not respecting LSRs choice of representation.
The change in 2011-10-06-ReusePhi.ll recovers a regression that
appeared when converting that test to opaque pointers.
Changes in various Thumb tests now compute the step outside the
loop instead of using add.w inside the loop, which is LSR's
preferred representation for this target.
Added:
Modified:
llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
llvm/test/CodeGen/Thumb2/LowOverheadLoops/memcall.ll
llvm/test/CodeGen/Thumb2/LowOverheadLoops/spillingmove.ll
llvm/test/CodeGen/Thumb2/mve-float16regloops.ll
llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
llvm/test/CodeGen/X86/dag-update-nodetomatch.ll
llvm/test/Transforms/LoopStrengthReduce/2011-10-06-ReusePhi.ll
Removed:
################################################################################
diff --git a/llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp b/llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
index 6200b4dcedeb13..fe79097c8a88e3 100644
--- a/llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
+++ b/llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
@@ -999,15 +999,8 @@ Instruction *SCEVExpander::getIVIncOperand(Instruction *IncV,
// allow any kind of GEP as long as it can be hoisted.
continue;
}
- // This must be a pointer addition of constants (pretty), which is already
- // handled, or some number of address-size elements (ugly). Ugly geps
- // have 2 operands. i1* is used by the expander to represent an
- // address-size element.
- if (IncV->getNumOperands() != 2)
- return nullptr;
- unsigned AS = cast<PointerType>(IncV->getType())->getAddressSpace();
- if (IncV->getType() != Type::getInt1PtrTy(SE.getContext(), AS)
- && IncV->getType() != Type::getInt8PtrTy(SE.getContext(), AS))
+ // GEPs produced by SCEVExpander use i8 element type.
+ if (!cast<GEPOperator>(IncV)->getSourceElementType()->isIntegerTy(8))
return nullptr;
break;
}
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/memcall.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/memcall.ll
index 59b32a3f441c1b..e0c045ba0440db 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/memcall.ll
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/memcall.ll
@@ -60,30 +60,31 @@ define void @test_memset(ptr nocapture %x, i32 %n, i32 %m) {
; CHECK-NEXT: cmp r1, #1
; CHECK-NEXT: it lt
; CHECK-NEXT: bxlt lr
-; CHECK-NEXT: .LBB1_1:
-; CHECK-NEXT: .save {r7, lr}
-; CHECK-NEXT: push {r7, lr}
+; CHECK-NEXT: .LBB1_1: @ %for.body.preheader
+; CHECK-NEXT: .save {r4, lr}
+; CHECK-NEXT: push {r4, lr}
+; CHECK-NEXT: lsl.w r12, r2, #2
; CHECK-NEXT: vmov.i32 q0, #0x0
; CHECK-NEXT: b .LBB1_2
; CHECK-NEXT: .LBB1_2: @ %for.body
; CHECK-NEXT: @ =>This Loop Header: Depth=1
; CHECK-NEXT: @ Child Loop BB1_4 Depth 2
-; CHECK-NEXT: mov r12, r0
+; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: wlstp.8 lr, r2, .LBB1_3
; CHECK-NEXT: b .LBB1_4
; CHECK-NEXT: .LBB1_3: @ %for.body
; CHECK-NEXT: @ in Loop: Header=BB1_2 Depth=1
-; CHECK-NEXT: add.w r0, r0, r2, lsl #2
+; CHECK-NEXT: add r0, r12
; CHECK-NEXT: subs r1, #1
; CHECK-NEXT: beq .LBB1_5
; CHECK-NEXT: b .LBB1_2
; CHECK-NEXT: .LBB1_4: @ Parent Loop BB1_2 Depth=1
; CHECK-NEXT: @ => This Inner Loop Header: Depth=2
-; CHECK-NEXT: vstrb.8 q0, [r12], #16
+; CHECK-NEXT: vstrb.8 q0, [r4], #16
; CHECK-NEXT: letp lr, .LBB1_4
; CHECK-NEXT: b .LBB1_3
; CHECK-NEXT: .LBB1_5:
-; CHECK-NEXT: pop.w {r7, lr}
+; CHECK-NEXT: pop.w {r4, lr}
; CHECK-NEXT: bx lr
entry:
%cmp5 = icmp sgt i32 %n, 0
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/spillingmove.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/spillingmove.ll
index be1f1de71be3da..14ceee58ef55cf 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/spillingmove.ll
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/spillingmove.ll
@@ -39,11 +39,12 @@ define void @__arm_2d_impl_rgb16_colour_filling_with_alpha(ptr noalias nocapture
; CHECK-NEXT: subs r3, #8
; CHECK-NEXT: movs r4, #1
; CHECK-NEXT: vdup.16 q0, r5
-; CHECK-NEXT: vdup.16 q5, r6
+; CHECK-NEXT: lsls r1, r1, #1
; CHECK-NEXT: add.w r3, r4, r3, lsr #3
; CHECK-NEXT: vstrw.32 q0, [sp, #48] @ 16-byte Spill
; CHECK-NEXT: vmov.i16 q0, #0xf800
; CHECK-NEXT: movs r4, #0
+; CHECK-NEXT: vdup.16 q5, r6
; CHECK-NEXT: vmov.i16 q7, #0x78
; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill
; CHECK-NEXT: vstrw.32 q2, [sp, #32] @ 16-byte Spill
@@ -95,7 +96,7 @@ define void @__arm_2d_impl_rgb16_colour_filling_with_alpha(ptr noalias nocapture
; CHECK-NEXT: @ %bb.5: @ %for.cond3.for.cond.cleanup7_crit_edge.us
; CHECK-NEXT: @ in Loop: Header=BB0_3 Depth=1
; CHECK-NEXT: adds r4, #1
-; CHECK-NEXT: add.w r0, r0, r1, lsl #1
+; CHECK-NEXT: add r0, r1
; CHECK-NEXT: cmp r4, r12
; CHECK-NEXT: bne .LBB0_3
; CHECK-NEXT: .LBB0_6:
@@ -219,6 +220,7 @@ define void @__arm_2d_impl_rgb16_colour_filling_with_alpha_sched(ptr noalias noc
; CHECK-NEXT: vstrw.32 q0, [sp, #32] @ 16-byte Spill
; CHECK-NEXT: vdup.16 q0, r5
; CHECK-NEXT: rsb.w r3, r7, #256
+; CHECK-NEXT: lsls r7, r1, #1
; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vdup.16 q0, r6
; CHECK-NEXT: vmov.i16 q2, #0xf8
@@ -265,8 +267,8 @@ define void @__arm_2d_impl_rgb16_colour_filling_with_alpha_sched(ptr noalias noc
; CHECK-NEXT: letp lr, .LBB1_4
; CHECK-NEXT: @ %bb.5: @ %for.cond3.for.cond.cleanup7_crit_edge.us
; CHECK-NEXT: @ in Loop: Header=BB1_3 Depth=1
-; CHECK-NEXT: add.w r0, r0, r1, lsl #1
; CHECK-NEXT: adds r4, #1
+; CHECK-NEXT: add r0, r7
; CHECK-NEXT: cmp r4, r12
; CHECK-NEXT: bne .LBB1_3
; CHECK-NEXT: @ %bb.6:
diff --git a/llvm/test/CodeGen/Thumb2/mve-float16regloops.ll b/llvm/test/CodeGen/Thumb2/mve-float16regloops.ll
index bf0b49d92f5004..25853063462e16 100644
--- a/llvm/test/CodeGen/Thumb2/mve-float16regloops.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-float16regloops.ll
@@ -663,34 +663,35 @@ for.cond.cleanup: ; preds = %vector.body, %entry
define dso_local void @test_nested(ptr noalias nocapture %pInT1, ptr noalias nocapture readonly %pOutT1, ptr noalias nocapture readonly %pPRT_in, ptr noalias nocapture readnone %pPRT_pDst, i32 %numRows, i32 %numCols, i32 %l) local_unnamed_addr {
; CHECK-LABEL: test_nested:
; CHECK: @ %bb.0: @ %for.body.us.preheader
-; CHECK-NEXT: .save {r4, r5, r7, lr}
-; CHECK-NEXT: push {r4, r5, r7, lr}
+; CHECK-NEXT: .save {r4, r5, r6, lr}
+; CHECK-NEXT: push {r4, r5, r6, lr}
; CHECK-NEXT: ldrd lr, r12, [sp, #16]
+; CHECK-NEXT: lsl.w r3, r12, #1
; CHECK-NEXT: .LBB14_1: @ %for.body.us
; CHECK-NEXT: @ =>This Loop Header: Depth=1
; CHECK-NEXT: @ Child Loop BB14_2 Depth 2
-; CHECK-NEXT: ldrh r3, [r1]
+; CHECK-NEXT: ldrh r4, [r1]
+; CHECK-NEXT: mov r5, r2
+; CHECK-NEXT: mov r6, r12
+; CHECK-NEXT: vdup.16 q0, r4
; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: mov r5, r12
-; CHECK-NEXT: vdup.16 q0, r3
-; CHECK-NEXT: add.w r3, r2, r12, lsl #1
; CHECK-NEXT: .LBB14_2: @ %vector.body
; CHECK-NEXT: @ Parent Loop BB14_1 Depth=1
; CHECK-NEXT: @ => This Inner Loop Header: Depth=2
-; CHECK-NEXT: vldrw.u32 q1, [r2], #16
+; CHECK-NEXT: vldrw.u32 q1, [r5], #16
; CHECK-NEXT: vldrw.u32 q2, [r4]
-; CHECK-NEXT: subs r5, #8
+; CHECK-NEXT: subs r6, #8
; CHECK-NEXT: vfms.f16 q2, q1, q0
; CHECK-NEXT: vstrb.8 q2, [r4], #16
; CHECK-NEXT: bne .LBB14_2
; CHECK-NEXT: @ %bb.3: @ %for.cond6.for.end_crit_edge.us
; CHECK-NEXT: @ in Loop: Header=BB14_1 Depth=1
-; CHECK-NEXT: add.w r0, r0, r12, lsl #1
+; CHECK-NEXT: add r0, r3
+; CHECK-NEXT: add r2, r3
; CHECK-NEXT: adds r1, #2
-; CHECK-NEXT: mov r2, r3
; CHECK-NEXT: le lr, .LBB14_1
; CHECK-NEXT: @ %bb.4: @ %for.end14
-; CHECK-NEXT: pop {r4, r5, r7, pc}
+; CHECK-NEXT: pop {r4, r5, r6, pc}
for.body.us.preheader:
%cmp = icmp sgt i32 %numRows, 0
tail call void @llvm.assume(i1 %cmp)
diff --git a/llvm/test/CodeGen/Thumb2/mve-float32regloops.ll b/llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
index 1364f1c2e82f8a..87f2e27341d6a5 100644
--- a/llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
@@ -663,34 +663,35 @@ for.cond.cleanup: ; preds = %vector.body, %entry
define dso_local void @test_nested(ptr noalias nocapture %pInT1, ptr noalias nocapture readonly %pOutT1, ptr noalias nocapture readonly %pPRT_in, ptr noalias nocapture readnone %pPRT_pDst, i32 %numRows, i32 %numCols, i32 %l) local_unnamed_addr {
; CHECK-LABEL: test_nested:
; CHECK: @ %bb.0: @ %for.body.us.preheader
-; CHECK-NEXT: .save {r4, r5, r7, lr}
-; CHECK-NEXT: push {r4, r5, r7, lr}
+; CHECK-NEXT: .save {r4, r5, r6, lr}
+; CHECK-NEXT: push {r4, r5, r6, lr}
; CHECK-NEXT: ldrd lr, r12, [sp, #16]
+; CHECK-NEXT: lsl.w r3, r12, #2
; CHECK-NEXT: .LBB14_1: @ %for.body.us
; CHECK-NEXT: @ =>This Loop Header: Depth=1
; CHECK-NEXT: @ Child Loop BB14_2 Depth 2
-; CHECK-NEXT: ldr r3, [r1]
+; CHECK-NEXT: ldr r4, [r1]
+; CHECK-NEXT: mov r5, r2
+; CHECK-NEXT: mov r6, r12
+; CHECK-NEXT: vdup.32 q0, r4
; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: mov r5, r12
-; CHECK-NEXT: vdup.32 q0, r3
-; CHECK-NEXT: add.w r3, r2, r12, lsl #2
; CHECK-NEXT: .LBB14_2: @ %vector.body
; CHECK-NEXT: @ Parent Loop BB14_1 Depth=1
; CHECK-NEXT: @ => This Inner Loop Header: Depth=2
-; CHECK-NEXT: vldrw.u32 q1, [r2], #16
+; CHECK-NEXT: vldrw.u32 q1, [r5], #16
; CHECK-NEXT: vldrw.u32 q2, [r4]
-; CHECK-NEXT: subs r5, #4
+; CHECK-NEXT: subs r6, #4
; CHECK-NEXT: vfms.f32 q2, q1, q0
; CHECK-NEXT: vstrb.8 q2, [r4], #16
; CHECK-NEXT: bne .LBB14_2
; CHECK-NEXT: @ %bb.3: @ %for.cond6.for.end_crit_edge.us
; CHECK-NEXT: @ in Loop: Header=BB14_1 Depth=1
-; CHECK-NEXT: add.w r0, r0, r12, lsl #2
+; CHECK-NEXT: add r0, r3
+; CHECK-NEXT: add r2, r3
; CHECK-NEXT: adds r1, #4
-; CHECK-NEXT: mov r2, r3
; CHECK-NEXT: le lr, .LBB14_1
; CHECK-NEXT: @ %bb.4: @ %for.end14
-; CHECK-NEXT: pop {r4, r5, r7, pc}
+; CHECK-NEXT: pop {r4, r5, r6, pc}
for.body.us.preheader:
%cmp = icmp sgt i32 %numRows, 0
tail call void @llvm.assume(i1 %cmp)
diff --git a/llvm/test/CodeGen/X86/dag-update-nodetomatch.ll b/llvm/test/CodeGen/X86/dag-update-nodetomatch.ll
index 1d026c40f1033e..adb7319fe80b11 100644
--- a/llvm/test/CodeGen/X86/dag-update-nodetomatch.ll
+++ b/llvm/test/CodeGen/X86/dag-update-nodetomatch.ll
@@ -96,17 +96,6 @@ entry:
define void @_Z2x6v() local_unnamed_addr {
; CHECK-LABEL: _Z2x6v:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movq x1 at GOTPCREL(%rip), %rax
-; CHECK-NEXT: movl (%rax), %esi
-; CHECK-NEXT: andl $511, %esi # imm = 0x1FF
-; CHECK-NEXT: leaq 1(%rsi), %rax
-; CHECK-NEXT: movq x4 at GOTPCREL(%rip), %rcx
-; CHECK-NEXT: movl %eax, (%rcx)
-; CHECK-NEXT: movq x3 at GOTPCREL(%rip), %rcx
-; CHECK-NEXT: movl (%rcx), %edx
-; CHECK-NEXT: testl %edx, %edx
-; CHECK-NEXT: je .LBB1_18
-; CHECK-NEXT: # %bb.1: # %for.cond1thread-pre-split.lr.ph
; CHECK-NEXT: pushq %rbp
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: pushq %r15
@@ -125,102 +114,112 @@ define void @_Z2x6v() local_unnamed_addr {
; CHECK-NEXT: .cfi_offset %r14, -32
; CHECK-NEXT: .cfi_offset %r15, -24
; CHECK-NEXT: .cfi_offset %rbp, -16
-; CHECK-NEXT: movq x5 at GOTPCREL(%rip), %rcx
-; CHECK-NEXT: movq (%rcx), %rdi
-; CHECK-NEXT: movl %edx, %ecx
-; CHECK-NEXT: notl %ecx
-; CHECK-NEXT: leaq 8(,%rcx,8), %rcx
-; CHECK-NEXT: imulq %rax, %rcx
-; CHECK-NEXT: addq %rdi, %rcx
-; CHECK-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT: movq x2 at GOTPCREL(%rip), %r9
-; CHECK-NEXT: movl (%r9), %ecx
-; CHECK-NEXT: leal 8(,%rsi,8), %r8d
-; CHECK-NEXT: movq %r8, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT: leaq 8(%rdi), %r8
-; CHECK-NEXT: movq %r8, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT: leaq 32(%rdi), %rbx
-; CHECK-NEXT: leaq 8(,%rsi,8), %r14
-; CHECK-NEXT: xorl %r15d, %r15d
-; CHECK-NEXT: movq x0 at GOTPCREL(%rip), %r12
-; CHECK-NEXT: movq %rdi, %r13
+; CHECK-NEXT: movq x1 at GOTPCREL(%rip), %rax
+; CHECK-NEXT: movl (%rax), %ebx
+; CHECK-NEXT: andl $511, %ebx # imm = 0x1FF
+; CHECK-NEXT: leaq 1(%rbx), %rax
+; CHECK-NEXT: movq x4 at GOTPCREL(%rip), %rcx
+; CHECK-NEXT: movl %eax, (%rcx)
+; CHECK-NEXT: movq x3 at GOTPCREL(%rip), %rcx
+; CHECK-NEXT: movl (%rcx), %ecx
+; CHECK-NEXT: testl %ecx, %ecx
+; CHECK-NEXT: je .LBB1_18
+; CHECK-NEXT: # %bb.1: # %for.cond1thread-pre-split.lr.ph
+; CHECK-NEXT: movq x5 at GOTPCREL(%rip), %rdx
+; CHECK-NEXT: movq (%rdx), %rsi
+; CHECK-NEXT: movl %ecx, %edx
+; CHECK-NEXT: notl %edx
+; CHECK-NEXT: leaq 8(,%rdx,8), %rdi
+; CHECK-NEXT: imulq %rax, %rdi
+; CHECK-NEXT: addq %rsi, %rdi
+; CHECK-NEXT: movq x2 at GOTPCREL(%rip), %r8
+; CHECK-NEXT: movl (%r8), %edx
+; CHECK-NEXT: leal 8(,%rbx,8), %eax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: leaq 8(%rsi), %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: leaq 32(%rsi), %r11
+; CHECK-NEXT: leaq 8(,%rbx,8), %rbx
+; CHECK-NEXT: xorl %r14d, %r14d
+; CHECK-NEXT: movq x0 at GOTPCREL(%rip), %r15
+; CHECK-NEXT: movq %rsi, %r12
; CHECK-NEXT: jmp .LBB1_2
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB1_15: # %for.cond1.for.inc3_crit_edge
; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1
-; CHECK-NEXT: movl %ecx, (%r9)
+; CHECK-NEXT: movl %edx, (%r8)
; CHECK-NEXT: .LBB1_16: # %for.inc3
; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1
-; CHECK-NEXT: incq %r15
-; CHECK-NEXT: addq %r14, %rbx
-; CHECK-NEXT: incl %edx
-; CHECK-NEXT: leaq (%r13,%rax,8), %r13
+; CHECK-NEXT: addq %rbx, %r12
+; CHECK-NEXT: incq %r14
+; CHECK-NEXT: addq %rbx, %r11
+; CHECK-NEXT: incl %ecx
; CHECK-NEXT: je .LBB1_17
; CHECK-NEXT: .LBB1_2: # %for.cond1thread-pre-split
; CHECK-NEXT: # =>This Loop Header: Depth=1
; CHECK-NEXT: # Child Loop BB1_12 Depth 2
; CHECK-NEXT: # Child Loop BB1_14 Depth 2
-; CHECK-NEXT: testl %ecx, %ecx
+; CHECK-NEXT: testl %edx, %edx
; CHECK-NEXT: jns .LBB1_16
; CHECK-NEXT: # %bb.3: # %for.body2.preheader
; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1
-; CHECK-NEXT: movslq %ecx, %rbp
-; CHECK-NEXT: testq %rbp, %rbp
-; CHECK-NEXT: movq $-1, %rsi
-; CHECK-NEXT: cmovnsq %rbp, %rsi
-; CHECK-NEXT: subq %rbp, %rsi
-; CHECK-NEXT: incq %rsi
-; CHECK-NEXT: cmpq $4, %rsi
+; CHECK-NEXT: movslq %edx, %r13
+; CHECK-NEXT: testq %r13, %r13
+; CHECK-NEXT: movq $-1, %rbp
+; CHECK-NEXT: cmovnsq %r13, %rbp
+; CHECK-NEXT: subq %r13, %rbp
+; CHECK-NEXT: incq %rbp
+; CHECK-NEXT: cmpq $4, %rbp
; CHECK-NEXT: jb .LBB1_14
; CHECK-NEXT: # %bb.4: # %min.iters.checked
; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1
-; CHECK-NEXT: movq %rsi, %rcx
-; CHECK-NEXT: andq $-4, %rcx
+; CHECK-NEXT: movq %rbp, %rdx
+; CHECK-NEXT: andq $-4, %rdx
; CHECK-NEXT: je .LBB1_14
; CHECK-NEXT: # %bb.5: # %vector.memcheck
; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1
-; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r10 # 8-byte Reload
-; CHECK-NEXT: imulq %r15, %r10
-; CHECK-NEXT: leaq (%rdi,%r10), %r11
-; CHECK-NEXT: leaq (%r11,%rbp,8), %r8
-; CHECK-NEXT: testq %rbp, %rbp
-; CHECK-NEXT: movq $-1, %r11
-; CHECK-NEXT: cmovnsq %rbp, %r11
-; CHECK-NEXT: cmpq %r12, %r8
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: imulq %r14, %rax
+; CHECK-NEXT: leaq (%rsi,%rax), %r10
+; CHECK-NEXT: leaq (%r10,%r13,8), %r9
+; CHECK-NEXT: testq %r13, %r13
+; CHECK-NEXT: movq $-1, %r10
+; CHECK-NEXT: cmovnsq %r13, %r10
+; CHECK-NEXT: cmpq %r15, %r9
; CHECK-NEXT: jae .LBB1_7
; CHECK-NEXT: # %bb.6: # %vector.memcheck
; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1
-; CHECK-NEXT: addq {{[-0-9]+}}(%r{{[sb]}}p), %r10 # 8-byte Folded Reload
-; CHECK-NEXT: leaq (%r10,%r11,8), %r8
-; CHECK-NEXT: cmpq %r12, %r8
+; CHECK-NEXT: addq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Folded Reload
+; CHECK-NEXT: leaq (%rax,%r10,8), %rax
+; CHECK-NEXT: cmpq %r15, %rax
; CHECK-NEXT: ja .LBB1_14
; CHECK-NEXT: .LBB1_7: # %vector.body.preheader
; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1
-; CHECK-NEXT: leaq -4(%rcx), %r11
-; CHECK-NEXT: btl $2, %r11d
+; CHECK-NEXT: leaq -4(%rdx), %rax
+; CHECK-NEXT: btl $2, %eax
; CHECK-NEXT: jb .LBB1_8
; CHECK-NEXT: # %bb.9: # %vector.body.prol.preheader
; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1
; CHECK-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
-; CHECK-NEXT: movdqu %xmm0, (%r13,%rbp,8)
-; CHECK-NEXT: movdqu %xmm0, 16(%r13,%rbp,8)
+; CHECK-NEXT: movdqu %xmm0, (%r12,%r13,8)
+; CHECK-NEXT: movdqu %xmm0, 16(%r12,%r13,8)
; CHECK-NEXT: movl $4, %r10d
-; CHECK-NEXT: shrq $2, %r11
+; CHECK-NEXT: shrq $2, %rax
; CHECK-NEXT: jne .LBB1_11
; CHECK-NEXT: jmp .LBB1_13
; CHECK-NEXT: .LBB1_8: # in Loop: Header=BB1_2 Depth=1
; CHECK-NEXT: xorl %r10d, %r10d
-; CHECK-NEXT: shrq $2, %r11
+; CHECK-NEXT: shrq $2, %rax
; CHECK-NEXT: je .LBB1_13
; CHECK-NEXT: .LBB1_11: # %vector.body.preheader.new
; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1
; CHECK-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
-; CHECK-NEXT: movq %r10, %r11
-; CHECK-NEXT: subq %rcx, %r11
-; CHECK-NEXT: addq %rbp, %r10
-; CHECK-NEXT: leaq (%rbx,%r10,8), %r10
+; CHECK-NEXT: movq %r10, %rax
+; CHECK-NEXT: subq %rdx, %rax
+; CHECK-NEXT: addq %r13, %r10
+; CHECK-NEXT: leaq (%r11,%r10,8), %r10
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB1_12: # %vector.body
; CHECK-NEXT: # Parent Loop BB1_2 Depth=1
@@ -230,31 +229,31 @@ define void @_Z2x6v() local_unnamed_addr {
; CHECK-NEXT: movdqu %xmm0, (%r10)
; CHECK-NEXT: movdqu %xmm0, 16(%r10)
; CHECK-NEXT: addq $64, %r10
-; CHECK-NEXT: addq $8, %r11
+; CHECK-NEXT: addq $8, %rax
; CHECK-NEXT: jne .LBB1_12
; CHECK-NEXT: .LBB1_13: # %middle.block
; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1
-; CHECK-NEXT: addq %rcx, %rbp
-; CHECK-NEXT: cmpq %rcx, %rsi
-; CHECK-NEXT: movq %rbp, %rcx
+; CHECK-NEXT: addq %rdx, %r13
+; CHECK-NEXT: cmpq %rdx, %rbp
+; CHECK-NEXT: movq %r13, %rdx
; CHECK-NEXT: je .LBB1_15
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB1_14: # %for.body2
; CHECK-NEXT: # Parent Loop BB1_2 Depth=1
; CHECK-NEXT: # => This Inner Loop Header: Depth=2
-; CHECK-NEXT: movq (%r12), %rcx
-; CHECK-NEXT: movq %rcx, (%r13,%rbp,8)
-; CHECK-NEXT: leaq 1(%rbp), %rcx
-; CHECK-NEXT: cmpq $-1, %rbp
-; CHECK-NEXT: movq %rcx, %rbp
+; CHECK-NEXT: movq (%r15), %rax
+; CHECK-NEXT: movq %rax, (%r12,%r13,8)
+; CHECK-NEXT: leaq 1(%r13), %rdx
+; CHECK-NEXT: cmpq $-1, %r13
+; CHECK-NEXT: movq %rdx, %r13
; CHECK-NEXT: jl .LBB1_14
; CHECK-NEXT: jmp .LBB1_15
; CHECK-NEXT: .LBB1_17: # %for.cond.for.end5_crit_edge
; CHECK-NEXT: movq x5 at GOTPCREL(%rip), %rax
-; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload
-; CHECK-NEXT: movq %rcx, (%rax)
+; CHECK-NEXT: movq %rdi, (%rax)
; CHECK-NEXT: movq x3 at GOTPCREL(%rip), %rax
; CHECK-NEXT: movl $0, (%rax)
+; CHECK-NEXT: .LBB1_18: # %for.end5
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: popq %r12
@@ -267,13 +266,6 @@ define void @_Z2x6v() local_unnamed_addr {
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: popq %rbp
; CHECK-NEXT: .cfi_def_cfa_offset 8
-; CHECK-NEXT: .cfi_restore %rbx
-; CHECK-NEXT: .cfi_restore %r12
-; CHECK-NEXT: .cfi_restore %r13
-; CHECK-NEXT: .cfi_restore %r14
-; CHECK-NEXT: .cfi_restore %r15
-; CHECK-NEXT: .cfi_restore %rbp
-; CHECK-NEXT: .LBB1_18: # %for.end5
; CHECK-NEXT: retq
entry:
%0 = load i32, ptr @x1, align 4
diff --git a/llvm/test/Transforms/LoopStrengthReduce/2011-10-06-ReusePhi.ll b/llvm/test/Transforms/LoopStrengthReduce/2011-10-06-ReusePhi.ll
index 92bc86b11b8383..f7b2ba30d15cae 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/2011-10-06-ReusePhi.ll
+++ b/llvm/test/Transforms/LoopStrengthReduce/2011-10-06-ReusePhi.ll
@@ -19,19 +19,21 @@ define float @test(ptr nocapture %A, ptr nocapture %B, i32 %N, i32 %IA, i32 %IB)
; CHECK: while.body.lr.ph:
; CHECK-NEXT: [[IDX_EXT:%.*]] = sext i32 [[IA]] to i64
; CHECK-NEXT: [[IDX_EXT2:%.*]] = sext i32 [[IB]] to i64
+; CHECK-NEXT: [[TMP0:%.*]] = shl nsw i64 [[IDX_EXT]], 2
+; CHECK-NEXT: [[TMP1:%.*]] = shl nsw i64 [[IDX_EXT2]], 2
; CHECK-NEXT: br label [[WHILE_BODY:%.*]]
; CHECK: while.body:
-; CHECK-NEXT: [[A_ADDR_05:%.*]] = phi ptr [ [[A]], [[WHILE_BODY_LR_PH]] ], [ [[ADD_PTR:%.*]], [[WHILE_BODY]] ]
-; CHECK-NEXT: [[B_ADDR_04:%.*]] = phi ptr [ [[B]], [[WHILE_BODY_LR_PH]] ], [ [[ADD_PTR3:%.*]], [[WHILE_BODY]] ]
+; CHECK-NEXT: [[LSR_IV1:%.*]] = phi ptr [ [[SCEVGEP2:%.*]], [[WHILE_BODY]] ], [ [[B]], [[WHILE_BODY_LR_PH]] ]
+; CHECK-NEXT: [[LSR_IV:%.*]] = phi ptr [ [[SCEVGEP:%.*]], [[WHILE_BODY]] ], [ [[A]], [[WHILE_BODY_LR_PH]] ]
; CHECK-NEXT: [[N_ADDR_03:%.*]] = phi i32 [ [[N]], [[WHILE_BODY_LR_PH]] ], [ [[SUB:%.*]], [[WHILE_BODY]] ]
; CHECK-NEXT: [[SUM0_02:%.*]] = phi float [ 0.000000e+00, [[WHILE_BODY_LR_PH]] ], [ [[ADD:%.*]], [[WHILE_BODY]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR_05]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[B_ADDR_04]], align 4
-; CHECK-NEXT: [[MUL:%.*]] = fmul float [[TMP0]], [[TMP1]]
+; CHECK-NEXT: [[TMP2:%.*]] = load float, ptr [[LSR_IV]], align 4
+; CHECK-NEXT: [[TMP3:%.*]] = load float, ptr [[LSR_IV1]], align 4
+; CHECK-NEXT: [[MUL:%.*]] = fmul float [[TMP2]], [[TMP3]]
; CHECK-NEXT: [[ADD]] = fadd float [[SUM0_02]], [[MUL]]
-; CHECK-NEXT: [[ADD_PTR]] = getelementptr inbounds float, ptr [[A_ADDR_05]], i64 [[IDX_EXT]]
-; CHECK-NEXT: [[ADD_PTR3]] = getelementptr inbounds float, ptr [[B_ADDR_04]], i64 [[IDX_EXT2]]
; CHECK-NEXT: [[SUB]] = add nsw i32 [[N_ADDR_03]], -1
+; CHECK-NEXT: [[SCEVGEP]] = getelementptr i8, ptr [[LSR_IV]], i64 [[TMP0]]
+; CHECK-NEXT: [[SCEVGEP2]] = getelementptr i8, ptr [[LSR_IV1]], i64 [[TMP1]]
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[SUB]], 0
; CHECK-NEXT: br i1 [[CMP]], label [[WHILE_BODY]], label [[WHILE_END_LOOPEXIT:%.*]]
; CHECK: while.end.loopexit:
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