[llvm] 86780f4 - [AArch64] Fix order of isReg and isDef checks in INSvi64 peephole.

[David Green via llvm-commits]

Author: David Green
Date: 2023-07-12T09:51:28+01:00
New Revision: 86780f49ef79ee3de93ee2fba6d3d6ad01ca4da3

URL: https://github.com/llvm/llvm-project/commit/86780f49ef79ee3de93ee2fba6d3d6ad01ca4da3
DIFF: https://github.com/llvm/llvm-project/commit/86780f49ef79ee3de93ee2fba6d3d6ad01ca4da3.diff

LOG: [AArch64] Fix order of isReg and isDef checks in INSvi64 peephole.

The isDef asserts that the operand isReg, so the checks need to happen in the
other order.

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
    llvm/test/CodeGen/AArch64/peephole-insvigpr.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp b/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
index 3421fbd9da70e9..87aa3b98d93826 100644
--- a/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
+++ b/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
@@ -612,7 +612,7 @@ bool AArch64MIPeepholeOpt::visitINSviGPR(MachineInstr &MI, unsigned Opc) {
 // register.
 static bool is64bitDefwithZeroHigh64bit(MachineInstr *MI,
                                         MachineRegisterInfo *MRI) {
-  if (!MI->getOperand(0).isDef() || !MI->getOperand(0).isReg())
+  if (!MI->getOperand(0).isReg() || !MI->getOperand(0).isDef())
     return false;
   const TargetRegisterClass *RC = MRI->getRegClass(MI->getOperand(0).getReg());
   if (RC != &AArch64::FPR64RegClass)

diff  --git a/llvm/test/CodeGen/AArch64/peephole-insvigpr.mir b/llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
index 0c1e618b8ea4ae..1c2fe27cdbc397 100644
--- a/llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
+++ b/llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
@@ -37,6 +37,11 @@
     ret void
   }
 
+  define void @asm(ptr %hist) {
+  entry:
+    ret void
+  }
+
   attributes #0 = { nocallback nofree nosync nounwind willreturn memory(none) }
 
 ...
@@ -450,3 +455,71 @@ body:             |
     RET_ReallyLR implicit $q0
 
 ...
+---
+name:            asm
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr64common, preferred-register: '' }
+  - { id: 1, class: fpr64, preferred-register: '' }
+  - { id: 2, class: gpr64all, preferred-register: '' }
+  - { id: 3, class: gpr64sp, preferred-register: '' }
+  - { id: 4, class: fpr128, preferred-register: '' }
+  - { id: 5, class: fpr64, preferred-register: '' }
+  - { id: 6, class: fpr128, preferred-register: '' }
+  - { id: 7, class: fpr128, preferred-register: '' }
+  - { id: 8, class: fpr128, preferred-register: '' }
+  - { id: 9, class: fpr128, preferred-register: '' }
+  - { id: 10, class: fpr128, preferred-register: '' }
+  - { id: 11, class: fpr64, preferred-register: '' }
+  - { id: 12, class: fpr64, preferred-register: '' }
+  - { id: 13, class: fpr128, preferred-register: '' }
+  - { id: 14, class: fpr128, preferred-register: '' }
+  - { id: 15, class: gpr32all, preferred-register: '' }
+  - { id: 16, class: fpr32, preferred-register: '' }
+liveins:
+  - { reg: '$x0', virtual-reg: '%0' }
+body:             |
+  bb.0.entry:
+    liveins: $x0
+
+    ; CHECK-LABEL: name: asm
+    ; CHECK: liveins: $x0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
+    ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[DEF]]
+    ; CHECK-NEXT: INLINEASM &"ldr ${0:s}, $1", 8 /* mayload attdialect */, 2359306 /* regdef:FPR64 */, def %1, 262158 /* mem:m */, killed [[COPY1]]
+    ; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[MOVIv2d_ns]].dsub
+    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], killed [[COPY2]], %subreg.dsub
+    ; CHECK-NEXT: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], %1, %subreg.dsub
+    ; CHECK-NEXT: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG1]], 1, killed [[INSERT_SUBREG]], 0
+    ; CHECK-NEXT: [[DEF3:%[0-9]+]]:fpr64 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[TBLv8i8One:%[0-9]+]]:fpr64 = TBLv8i8One killed [[INSvi64lane]], killed [[DEF3]]
+    ; CHECK-NEXT: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], killed [[TBLv8i8One]], %subreg.dsub
+    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[INSERT_SUBREG2]].ssub
+    ; CHECK-NEXT: STRSui killed [[COPY3]], [[COPY]], 0 :: (store (s32) into %ir.hist)
+    ; CHECK-NEXT: RET_ReallyLR
+    %0:gpr64common = COPY $x0
+    %2:gpr64all = IMPLICIT_DEF
+    %3:gpr64sp = COPY %2
+    INLINEASM &"ldr ${0:s}, $1", 8 /* mayload attdialect */, 2359306 /* regdef:FPR64 */, def %1, 262158 /* mem:m */, killed %3
+    %4:fpr128 = MOVIv2d_ns 0
+    %5:fpr64 = COPY %4.dsub
+    %7:fpr128 = IMPLICIT_DEF
+    %6:fpr128 = INSERT_SUBREG %7, killed %5, %subreg.dsub
+    %9:fpr128 = IMPLICIT_DEF
+    %8:fpr128 = INSERT_SUBREG %9, %1, %subreg.dsub
+    %10:fpr128 = INSvi64lane %8, 1, killed %6, 0
+    %12:fpr64 = IMPLICIT_DEF
+    %11:fpr64 = TBLv8i8One killed %10, killed %12
+    %14:fpr128 = IMPLICIT_DEF
+    %13:fpr128 = INSERT_SUBREG %14, killed %11, %subreg.dsub
+    %16:fpr32 = COPY %13.ssub
+    STRSui killed %16, %0, 0 :: (store (s32) into %ir.hist)
+    RET_ReallyLR
+
+...