[PATCH] D155044: [RISCV] Lower inline asm constraints vi, vj and vk.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:16095
+  } else {
+    if (Constraint == "vi") {
+      if (auto *C = dyn_cast<ConstantSDNode>(Op)) {
----------------
Can we merge this `if` into the previous `else` so we have

```
if (Constraint.length() == 1) {
   ...
} else if (Constraint == "vi") {
  ...
} else if (Constraint == "vk") {
 ...
} else if (Constraint == "vj") {
 ...
}
```


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155044/new/

https://reviews.llvm.org/D155044