[PATCH] D155046: [RISCV] Clear kill flags when forming FMA instructions in MachineCombiner.

[Craig Topper via Phabricator via llvm-commits]

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If the operands to the mul have other uses we may be extending their
live range past a kill flag.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D155046

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/test/CodeGen/RISCV/machine-combiner.mir


Index: llvm/test/CodeGen/RISCV/machine-combiner.mir
===================================================================
--- llvm/test/CodeGen/RISCV/machine-combiner.mir
+++ llvm/test/CodeGen/RISCV/machine-combiner.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
-# RUN: llc %s -mtriple=riscv64 -mattr=+f -run-pass=machine-combiner \
+# RUN: llc %s -o - -mtriple=riscv64 -mattr=+f -run-pass=machine-combiner \
 # RUN:   -verify-machineinstrs | FileCheck %s
 
 --- |
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1659,6 +1659,9 @@
   bool Mul2IsKill = Mul2.isKill();
   bool AddendIsKill = Addend.isKill();
 
+  // We need to clear kill flags since we may be extending the live range past
+  // a kill. If the mul had kill flags, we can preserve those since we know
+  // where the previous range stopped.
   MRI.clearKillFlags(Mul1.getReg());
   MRI.clearKillFlags(Mul2.getReg());
 


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