[PATCH] D155044: [RISCV] Lower inline asm constraints vi, vj and vk.

[Yeting Kuo via Phabricator via llvm-commits]

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This validate and lower arguments to inline asm nodes which have the constraints vi, vi and vk, with the following semantics (equivalent to GCC):
vi: vector 5-bit signed immediate.
vj: vector negated 5-bit signed immediate.
vk: vector 5-bit unsigned immediate.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D155044

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/inline-asm-invalid.ll
  llvm/test/CodeGen/RISCV/rvv/inline-asm.ll

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