[PATCH] D155040: [LegalizeDAG] Prevent LegalizeLoadOps from creating extloads that mix int and fp types.

[Craig Topper via Phabricator via llvm-commits]

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For RISC-V, getRegisterType for fp16 returns i16. i16->fp64 extload
is considered legal because the LoadExtActions defaults to Legal
for all entries. Only fp/fp and int/int entries are changed to
Expand fore RISC-V.

This patch detects the FP-ness has changed and won't try to call
isLoadExtLegal.

Alternatively, we could add Expand for int/fp and fp/int, but that
seemed a little silly.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D155040

Files:
  llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
  llvm/test/CodeGen/RISCV/pr63816.ll

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