[PATCH] D154947: [AArch64] Split lowerVectorFCMP combine

[Amara Emerson via Phabricator via llvm-commits]

aemerson accepted this revision.
aemerson added a comment.

LGTM with nit.



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Comment at: llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp:977-981
   Register RHS = MI.getOperand(3).getReg();
+  Register LHS = MI.getOperand(2).getReg();
+  Register Dst = MI.getOperand(0).getReg();
+  const auto Pred =
+      static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
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Could you re-order these into Dst. LHS then RHS. You can use `GFCmp` here to simplify accessing the regs and predicate.


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