[llvm] 8480fed - [RISCV] Remove SiFive7GetCyclesWidening from RISCVSchedSiFive7.td.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-07-11T12:17:10-07:00
New Revision: 8480fed422a459c983ca8a4e6076229dc5ba8979

URL: https://github.com/llvm/llvm-project/commit/8480fed422a459c983ca8a4e6076229dc5ba8979
DIFF: https://github.com/llvm/llvm-project/commit/8480fed422a459c983ca8a4e6076229dc5ba8979.diff

LOG: [RISCV] Remove SiFive7GetCyclesWidening from RISCVSchedSiFive7.td.

It's identical to SiFive7GetCyclesDefault.

Differential Revision: https://reviews.llvm.org/D155002

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index 2db8cd015b51ae..956bbb3f97e1a0 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -40,17 +40,6 @@ class SiFive7GetCyclesDefault<string mx> {
   );
 }
 
-class SiFive7GetCyclesWidening<string mx> {
-  int c = !cond(
-    !eq(mx, "M1") : 2,
-    !eq(mx, "M2") : 4,
-    !eq(mx, "M4") : 8,
-    !eq(mx, "MF2") : 1,
-    !eq(mx, "MF4") : 1,
-    !eq(mx, "MF8") : 1
-  );
-}
-
 class SiFive7GetCyclesNarrowing<string mx> {
   int c = !cond(
     !eq(mx, "M1") : 4,
@@ -649,7 +638,7 @@ foreach mx = SchedMxList in {
 
 // Widening
 foreach mx = SchedMxListW in {
-  defvar Cycles = SiFive7GetCyclesWidening<mx>.c;
+  defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
   defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListW>.c;
   let Latency = 8, ResourceCycles = [Cycles] in {
     defm "" : LMULWriteResMX<"WriteVIWALUV",    [SiFive7VA], mx, IsWorstCase>;
@@ -745,14 +734,14 @@ foreach mx = SchedMxListF in {
 
 // Widening
 foreach mx = SchedMxListW in {
-  defvar Cycles = SiFive7GetCyclesWidening<mx>.c;
+  defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
   defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListW>.c;
   let Latency = 8, ResourceCycles = [Cycles] in {
     defm "" : LMULWriteResMX<"WriteVFWCvtIToFV", [SiFive7VA], mx, IsWorstCase>;
   }
 }
 foreach mx = SchedMxListFW in {
-  defvar Cycles = SiFive7GetCyclesWidening<mx>.c;
+  defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
   defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListFW>.c;
   let Latency = 8, ResourceCycles = [Cycles] in {
     defm "" : LMULWriteResMX<"WriteVFWALUV",     [SiFive7VA], mx, IsWorstCase>;