[PATCH] D154245: [RISCV] Remove legacy TA/TU pseudo distinction for binary instructions

[Philip Reames via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG5cd41dc62db7: [RISCV] Remove legacy TA/TU pseudo distinction for binary instructions (authored by reames).

Changed prior to commit:
  https://reviews.llvm.org/D154245?vs=538653&id=539176#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154245/new/

https://reviews.llvm.org/D154245

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/test/CodeGen/RISCV/double_reduct.ll
  llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
  llvm/test/CodeGen/RISCV/rvv/active_lane_mask.ll
  llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
  llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
  llvm/test/CodeGen/RISCV/rvv/commuted-op-indices-regression.mir
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmf.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-transpose.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
  llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
  llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
  llvm/test/CodeGen/RISCV/rvv/reg-coalescing.mir
  llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
  llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll
  llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
  llvm/test/CodeGen/RISCV/rvv/sshl_sat_vec.ll
  llvm/test/CodeGen/RISCV/rvv/stepvector.ll
  llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir
  llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
  llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
  llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
  llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
  llvm/test/CodeGen/RISCV/rvv/vxrm.mir
  llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll

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