[PATCH] D154920: [RISCV] Constrain register class before replaceRegWith in RISCVMergeBaseOffset.

[Craig Topper via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG11051d7d864b: [RISCV] Constrain register class before replaceRegWith in RISCVMergeBaseOffset. (authored by craig.topper).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154920/new/

https://reviews.llvm.org/D154920

Files:
  llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp


Index: llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+++ llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
@@ -140,6 +140,8 @@
   if (Hi.getOpcode() != RISCV::AUIPC)
     Lo.getOperand(2).setOffset(Offset);
   // Delete the tail instruction.
+  MRI->constrainRegClass(Lo.getOperand(0).getReg(),
+                         MRI->getRegClass(Tail.getOperand(0).getReg()));
   MRI->replaceRegWith(Tail.getOperand(0).getReg(), Lo.getOperand(0).getReg());
   Tail.eraseFromParent();
   LLVM_DEBUG(dbgs() << "  Merged offset " << Offset << " into base.\n"


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D154920.539170.patch
Type: text/x-patch
Size: 665 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230711/a5b7852d/attachment.bin>