[llvm] 11051d7 - [RISCV] Constrain register class before replaceRegWith in RISCVMergeBaseOffset.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-07-11T09:53:56-07:00
New Revision: 11051d7d864bc4afdb9ec85b20825fcbf5a40022

URL: https://github.com/llvm/llvm-project/commit/11051d7d864bc4afdb9ec85b20825fcbf5a40022
DIFF: https://github.com/llvm/llvm-project/commit/11051d7d864bc4afdb9ec85b20825fcbf5a40022.diff

LOG: [RISCV] Constrain register class before replaceRegWith in RISCVMergeBaseOffset.

The register being replaced might have a more restrictive register
class due to requirements of the using instruction. We should
constrain the register class to preserve any restrictions.

This was found in our downstream on a custom instruction. I don't
have a test case for upstream currently.

Differential Revision: https://reviews.llvm.org/D154920

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp b/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
index a2b3065fdefbea..855322b981fb63 100644
--- a/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+++ b/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
@@ -140,6 +140,8 @@ void RISCVMergeBaseOffsetOpt::foldOffset(MachineInstr &Hi, MachineInstr &Lo,
   if (Hi.getOpcode() != RISCV::AUIPC)
     Lo.getOperand(2).setOffset(Offset);
   // Delete the tail instruction.
+  MRI->constrainRegClass(Lo.getOperand(0).getReg(),
+                         MRI->getRegClass(Tail.getOperand(0).getReg()));
   MRI->replaceRegWith(Tail.getOperand(0).getReg(), Lo.getOperand(0).getReg());
   Tail.eraseFromParent();
   LLVM_DEBUG(dbgs() << "  Merged offset " << Offset << " into base.\n"