[PATCH] D154960: [DAG] Use legal shift amount type in DAGTypeLegalizer::JoinIntegers

[Jay Foad via Phabricator via llvm-commits]

foad created this revision.
Herald added subscribers: bzcheeseman, StephenFan, kerbowa, hiraditya, tpr, jvesely.
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Documentation for TargetLowering::getShiftAmountTy says that LegalTypes
should generally be true during type legalization, so this patch does
that.

On AMDGPU the effect is that we use i32 (a sane type) instead of i64
(pointer sized type) for more shift amounts, which in turn allows more
formation of rotates and funnel shifts pre-legalization.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D154960

Files:
  llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
  llvm/test/CodeGen/AMDGPU/bswap.ll
  llvm/test/CodeGen/AMDGPU/build_vector.ll
  llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
  llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
  llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
  llvm/test/CodeGen/AMDGPU/fneg.ll
  llvm/test/CodeGen/AMDGPU/idot4u.ll
  llvm/test/CodeGen/AMDGPU/idot8s.ll
  llvm/test/CodeGen/AMDGPU/idot8u.ll
  llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
  llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
  llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
  llvm/test/CodeGen/AMDGPU/permute_i8.ll
  llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
  llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
  llvm/test/CodeGen/AMDGPU/usubsat.ll

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