[llvm] b515133 - [RISCV] Merge rv32/rv64 vector reduction intrinsic tests that have the same content. NFC.
Jim Lin via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 11 04:06:00 PDT 2023
Author: Jim Lin
Date: 2023-07-11T19:04:56+08:00
New Revision: b51513308898e548db24d89f9a30fe590d639f66
URL: https://github.com/llvm/llvm-project/commit/b51513308898e548db24d89f9a30fe590d639f66
DIFF: https://github.com/llvm/llvm-project/commit/b51513308898e548db24d89f9a30fe590d639f66.diff
LOG: [RISCV] Merge rv32/rv64 vector reduction intrinsic tests that have the same content. NFC.
Added:
llvm/test/CodeGen/RISCV/rvv/vredand.ll
llvm/test/CodeGen/RISCV/rvv/vredmax.ll
llvm/test/CodeGen/RISCV/rvv/vredmaxu.ll
llvm/test/CodeGen/RISCV/rvv/vredmin.ll
llvm/test/CodeGen/RISCV/rvv/vredminu.ll
llvm/test/CodeGen/RISCV/rvv/vredor.ll
llvm/test/CodeGen/RISCV/rvv/vredsum.ll
llvm/test/CodeGen/RISCV/rvv/vredxor.ll
Modified:
Removed:
llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll
deleted file mode 100644
index 404768d718dd11..00000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll
+++ /dev/null
@@ -1,968 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
-declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8(
- <vscale x 8 x i8>,
- <vscale x 1 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv1i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vredand.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8(
- <vscale x 8 x i8> %0,
- <vscale x 1 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv1i8(
- <vscale x 8 x i8>,
- <vscale x 1 x i8>,
- <vscale x 8 x i8>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv1i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv1i8(
- <vscale x 8 x i8> %0,
- <vscale x 1 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8(
- <vscale x 8 x i8>,
- <vscale x 2 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv2i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vredand.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8(
- <vscale x 8 x i8> %0,
- <vscale x 2 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv2i8(
- <vscale x 8 x i8>,
- <vscale x 2 x i8>,
- <vscale x 8 x i8>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv2i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv2i8(
- <vscale x 8 x i8> %0,
- <vscale x 2 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8(
- <vscale x 8 x i8>,
- <vscale x 4 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv4i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vredand.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8(
- <vscale x 8 x i8> %0,
- <vscale x 4 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv4i8(
- <vscale x 8 x i8>,
- <vscale x 4 x i8>,
- <vscale x 8 x i8>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv4i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv4i8(
- <vscale x 8 x i8> %0,
- <vscale x 4 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv8i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vredand.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv8i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv8i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv8i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8(
- <vscale x 8 x i8>,
- <vscale x 16 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv16i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vredand.vs v8, v10, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8(
- <vscale x 8 x i8> %0,
- <vscale x 16 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv16i8(
- <vscale x 8 x i8>,
- <vscale x 16 x i8>,
- <vscale x 8 x i8>,
- <vscale x 16 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv16i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vredand.vs v8, v10, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv16i8(
- <vscale x 8 x i8> %0,
- <vscale x 16 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 16 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8(
- <vscale x 8 x i8>,
- <vscale x 32 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv32i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vredand.vs v8, v12, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8(
- <vscale x 8 x i8> %0,
- <vscale x 32 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv32i8(
- <vscale x 8 x i8>,
- <vscale x 32 x i8>,
- <vscale x 8 x i8>,
- <vscale x 32 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv32i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vredand.vs v8, v12, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv32i8(
- <vscale x 8 x i8> %0,
- <vscale x 32 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 32 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16(
- <vscale x 4 x i16>,
- <vscale x 1 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv1i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vredand.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16(
- <vscale x 4 x i16> %0,
- <vscale x 1 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv1i16(
- <vscale x 4 x i16>,
- <vscale x 1 x i16>,
- <vscale x 4 x i16>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv1i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv1i16(
- <vscale x 4 x i16> %0,
- <vscale x 1 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv2i16(
- <vscale x 4 x i16>,
- <vscale x 2 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv2i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vredand.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv2i16(
- <vscale x 4 x i16> %0,
- <vscale x 2 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv2i16(
- <vscale x 4 x i16>,
- <vscale x 2 x i16>,
- <vscale x 4 x i16>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv2i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv2i16(
- <vscale x 4 x i16> %0,
- <vscale x 2 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv4i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv4i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vredand.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv4i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv4i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv4i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv4i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv8i16(
- <vscale x 4 x i16>,
- <vscale x 8 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv8i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vredand.vs v8, v10, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv8i16(
- <vscale x 4 x i16> %0,
- <vscale x 8 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv8i16(
- <vscale x 4 x i16>,
- <vscale x 8 x i16>,
- <vscale x 4 x i16>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv8i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vredand.vs v8, v10, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv8i16(
- <vscale x 4 x i16> %0,
- <vscale x 8 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv16i16(
- <vscale x 4 x i16>,
- <vscale x 16 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv16i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vredand.vs v8, v12, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv16i16(
- <vscale x 4 x i16> %0,
- <vscale x 16 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv16i16(
- <vscale x 4 x i16>,
- <vscale x 16 x i16>,
- <vscale x 4 x i16>,
- <vscale x 16 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv16i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vredand.vs v8, v12, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv16i16(
- <vscale x 4 x i16> %0,
- <vscale x 16 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 16 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv32i16(
- <vscale x 4 x i16>,
- <vscale x 32 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv32i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vredand.vs v8, v16, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv32i16(
- <vscale x 4 x i16> %0,
- <vscale x 32 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv32i16(
- <vscale x 4 x i16>,
- <vscale x 32 x i16>,
- <vscale x 4 x i16>,
- <vscale x 32 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv32i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vredand.vs v8, v16, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv32i16(
- <vscale x 4 x i16> %0,
- <vscale x 32 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 32 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv1i32(
- <vscale x 2 x i32>,
- <vscale x 1 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv1i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vredand.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv1i32(
- <vscale x 2 x i32> %0,
- <vscale x 1 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv1i32(
- <vscale x 2 x i32>,
- <vscale x 1 x i32>,
- <vscale x 2 x i32>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv1i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv1i32(
- <vscale x 2 x i32> %0,
- <vscale x 1 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv2i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vredand.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv2i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv2i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv2i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv4i32(
- <vscale x 2 x i32>,
- <vscale x 4 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv4i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vredand.vs v8, v10, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv4i32(
- <vscale x 2 x i32> %0,
- <vscale x 4 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv4i32(
- <vscale x 2 x i32>,
- <vscale x 4 x i32>,
- <vscale x 2 x i32>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv4i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vredand.vs v8, v10, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv4i32(
- <vscale x 2 x i32> %0,
- <vscale x 4 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv8i32(
- <vscale x 2 x i32>,
- <vscale x 8 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv8i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vredand.vs v8, v12, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv8i32(
- <vscale x 2 x i32> %0,
- <vscale x 8 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv8i32(
- <vscale x 2 x i32>,
- <vscale x 8 x i32>,
- <vscale x 2 x i32>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv8i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vredand.vs v8, v12, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv8i32(
- <vscale x 2 x i32> %0,
- <vscale x 8 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv16i32(
- <vscale x 2 x i32>,
- <vscale x 16 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv16i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vredand.vs v8, v16, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv16i32(
- <vscale x 2 x i32> %0,
- <vscale x 16 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv16i32(
- <vscale x 2 x i32>,
- <vscale x 16 x i32>,
- <vscale x 2 x i32>,
- <vscale x 16 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv16i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vredand.vs v8, v16, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv16i32(
- <vscale x 2 x i32> %0,
- <vscale x 16 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 16 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv1i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredand_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredand_vs_nxv1i64_nxv1i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vredand.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv1i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- <vscale x 1 x i64> %2,
- i64 %3)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv1i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredand_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv1i64_nxv1i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv1i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv2i64(
- <vscale x 1 x i64>,
- <vscale x 2 x i64>,
- <vscale x 1 x i64>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredand_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredand_vs_nxv1i64_nxv2i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vredand.vs v8, v10, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv2i64(
- <vscale x 1 x i64> %0,
- <vscale x 2 x i64> %1,
- <vscale x 1 x i64> %2,
- i64 %3)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv2i64(
- <vscale x 1 x i64>,
- <vscale x 2 x i64>,
- <vscale x 1 x i64>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredand_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv1i64_nxv2i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vredand.vs v8, v10, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv2i64(
- <vscale x 1 x i64> %0,
- <vscale x 2 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv4i64(
- <vscale x 1 x i64>,
- <vscale x 4 x i64>,
- <vscale x 1 x i64>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredand_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredand_vs_nxv1i64_nxv4i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vredand.vs v8, v12, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv4i64(
- <vscale x 1 x i64> %0,
- <vscale x 4 x i64> %1,
- <vscale x 1 x i64> %2,
- i64 %3)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv4i64(
- <vscale x 1 x i64>,
- <vscale x 4 x i64>,
- <vscale x 1 x i64>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredand_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv1i64_nxv4i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vredand.vs v8, v12, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv4i64(
- <vscale x 1 x i64> %0,
- <vscale x 4 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv8i64(
- <vscale x 1 x i64>,
- <vscale x 8 x i64>,
- <vscale x 1 x i64>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredand_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredand_vs_nxv1i64_nxv8i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vredand.vs v8, v16, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv8i64(
- <vscale x 1 x i64> %0,
- <vscale x 8 x i64> %1,
- <vscale x 1 x i64> %2,
- i64 %3)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv8i64(
- <vscale x 1 x i64>,
- <vscale x 8 x i64>,
- <vscale x 1 x i64>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredand_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv1i64_nxv8i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vredand.vs v8, v16, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv8i64(
- <vscale x 1 x i64> %0,
- <vscale x 8 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i64> %a
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vredand.ll
similarity index 90%
rename from llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll
rename to llvm/test/CodeGen/RISCV/rvv/vredand.ll
index b9a6c8d07a9b4d..a46dab75a460a3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vredand.ll
@@ -1,13 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s
declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8(
<vscale x 8 x i8>,
<vscale x 1 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
@@ -18,7 +20,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 1 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -28,9 +30,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 8 x i8>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
@@ -42,7 +44,7 @@ entry:
<vscale x 1 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -51,9 +53,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8(
<vscale x 8 x i8>,
<vscale x 2 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
@@ -64,7 +66,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 2 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -74,9 +76,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 8 x i8>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
@@ -88,7 +90,7 @@ entry:
<vscale x 2 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -97,9 +99,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8(
<vscale x 8 x i8>,
<vscale x 4 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
@@ -110,7 +112,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 4 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -120,9 +122,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 8 x i8>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
@@ -134,7 +136,7 @@ entry:
<vscale x 4 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -143,9 +145,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
@@ -156,7 +158,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -166,9 +168,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
@@ -180,7 +182,7 @@ entry:
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -189,9 +191,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8(
<vscale x 8 x i8>,
<vscale x 16 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
@@ -202,7 +204,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 16 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -212,9 +214,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 8 x i8>,
<vscale x 16 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
@@ -226,7 +228,7 @@ entry:
<vscale x 16 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 16 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -235,9 +237,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8(
<vscale x 8 x i8>,
<vscale x 32 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
@@ -248,7 +250,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 32 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -258,9 +260,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 8 x i8>,
<vscale x 32 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
@@ -272,7 +274,7 @@ entry:
<vscale x 32 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 32 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -281,9 +283,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16(
<vscale x 4 x i16>,
<vscale x 1 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
@@ -294,7 +296,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 1 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -304,9 +306,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 4 x i16>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
@@ -318,7 +320,7 @@ entry:
<vscale x 1 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -327,9 +329,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv2i16(
<vscale x 4 x i16>,
<vscale x 2 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
@@ -340,7 +342,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 2 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -350,9 +352,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 4 x i16>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
@@ -364,7 +366,7 @@ entry:
<vscale x 2 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -373,9 +375,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
@@ -386,7 +388,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -396,9 +398,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
@@ -410,7 +412,7 @@ entry:
<vscale x 4 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -419,9 +421,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv8i16(
<vscale x 4 x i16>,
<vscale x 8 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
@@ -432,7 +434,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 8 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -442,9 +444,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 4 x i16>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
@@ -456,7 +458,7 @@ entry:
<vscale x 8 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -465,9 +467,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv16i16(
<vscale x 4 x i16>,
<vscale x 16 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
@@ -478,7 +480,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 16 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -488,9 +490,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 4 x i16>,
<vscale x 16 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
@@ -502,7 +504,7 @@ entry:
<vscale x 16 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 16 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -511,9 +513,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv32i16(
<vscale x 4 x i16>,
<vscale x 32 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
@@ -524,7 +526,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 32 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -534,9 +536,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 4 x i16>,
<vscale x 32 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
@@ -548,7 +550,7 @@ entry:
<vscale x 32 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 32 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -557,9 +559,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv1i32(
<vscale x 2 x i32>,
<vscale x 1 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
@@ -570,7 +572,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 1 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -580,9 +582,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 2 x i32>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
@@ -594,7 +596,7 @@ entry:
<vscale x 1 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -603,9 +605,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
@@ -616,7 +618,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -626,9 +628,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
@@ -640,7 +642,7 @@ entry:
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -649,9 +651,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv4i32(
<vscale x 2 x i32>,
<vscale x 4 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
@@ -662,7 +664,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 4 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -672,9 +674,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 2 x i32>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
@@ -686,7 +688,7 @@ entry:
<vscale x 4 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -695,9 +697,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv8i32(
<vscale x 2 x i32>,
<vscale x 8 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
@@ -708,7 +710,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 8 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -718,9 +720,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 2 x i32>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
@@ -732,7 +734,7 @@ entry:
<vscale x 8 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -741,9 +743,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv16i32(
<vscale x 2 x i32>,
<vscale x 16 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
@@ -754,7 +756,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 16 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -764,9 +766,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 2 x i32>,
<vscale x 16 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
@@ -778,7 +780,7 @@ entry:
<vscale x 16 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 16 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -787,9 +789,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i64>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredand_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredand_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
@@ -800,7 +802,7 @@ entry:
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
<vscale x 1 x i64> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 1 x i64> %a
}
@@ -810,9 +812,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredand_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredand_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
@@ -824,7 +826,7 @@ entry:
<vscale x 1 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i64> %a
}
@@ -833,9 +835,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv2i64(
<vscale x 1 x i64>,
<vscale x 2 x i64>,
<vscale x 1 x i64>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredand_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredand_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
@@ -846,7 +848,7 @@ entry:
<vscale x 1 x i64> %0,
<vscale x 2 x i64> %1,
<vscale x 1 x i64> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 1 x i64> %a
}
@@ -856,9 +858,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 1 x i64>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredand_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredand_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
@@ -870,7 +872,7 @@ entry:
<vscale x 2 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i64> %a
}
@@ -879,9 +881,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv4i64(
<vscale x 1 x i64>,
<vscale x 4 x i64>,
<vscale x 1 x i64>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredand_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredand_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
@@ -892,7 +894,7 @@ entry:
<vscale x 1 x i64> %0,
<vscale x 4 x i64> %1,
<vscale x 1 x i64> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 1 x i64> %a
}
@@ -902,9 +904,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 1 x i64>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredand_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredand_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
@@ -916,7 +918,7 @@ entry:
<vscale x 4 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i64> %a
}
@@ -925,9 +927,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv8i64(
<vscale x 1 x i64>,
<vscale x 8 x i64>,
<vscale x 1 x i64>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredand_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredand_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
@@ -938,7 +940,7 @@ entry:
<vscale x 1 x i64> %0,
<vscale x 8 x i64> %1,
<vscale x 1 x i64> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 1 x i64> %a
}
@@ -948,9 +950,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 1 x i64>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredand_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredand_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
@@ -962,7 +964,7 @@ entry:
<vscale x 8 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i64> %a
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll
deleted file mode 100644
index 02b9f5f537ef45..00000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll
+++ /dev/null
@@ -1,968 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
-declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8(
- <vscale x 8 x i8>,
- <vscale x 1 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv1i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8(
- <vscale x 8 x i8> %0,
- <vscale x 1 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv1i8(
- <vscale x 8 x i8>,
- <vscale x 1 x i8>,
- <vscale x 8 x i8>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv1i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv1i8(
- <vscale x 8 x i8> %0,
- <vscale x 1 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8(
- <vscale x 8 x i8>,
- <vscale x 2 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv2i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8(
- <vscale x 8 x i8> %0,
- <vscale x 2 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv2i8(
- <vscale x 8 x i8>,
- <vscale x 2 x i8>,
- <vscale x 8 x i8>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv2i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv2i8(
- <vscale x 8 x i8> %0,
- <vscale x 2 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8(
- <vscale x 8 x i8>,
- <vscale x 4 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv4i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8(
- <vscale x 8 x i8> %0,
- <vscale x 4 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv4i8(
- <vscale x 8 x i8>,
- <vscale x 4 x i8>,
- <vscale x 8 x i8>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv4i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv4i8(
- <vscale x 8 x i8> %0,
- <vscale x 4 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv8i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv8i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv8i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv8i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8(
- <vscale x 8 x i8>,
- <vscale x 16 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv16i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v10, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8(
- <vscale x 8 x i8> %0,
- <vscale x 16 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv16i8(
- <vscale x 8 x i8>,
- <vscale x 16 x i8>,
- <vscale x 8 x i8>,
- <vscale x 16 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv16i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v10, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv16i8(
- <vscale x 8 x i8> %0,
- <vscale x 16 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 16 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8(
- <vscale x 8 x i8>,
- <vscale x 32 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv32i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v12, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8(
- <vscale x 8 x i8> %0,
- <vscale x 32 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv32i8(
- <vscale x 8 x i8>,
- <vscale x 32 x i8>,
- <vscale x 8 x i8>,
- <vscale x 32 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv32i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v12, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv32i8(
- <vscale x 8 x i8> %0,
- <vscale x 32 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 32 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16(
- <vscale x 4 x i16>,
- <vscale x 1 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv1i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16(
- <vscale x 4 x i16> %0,
- <vscale x 1 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv1i16(
- <vscale x 4 x i16>,
- <vscale x 1 x i16>,
- <vscale x 4 x i16>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv1i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv1i16(
- <vscale x 4 x i16> %0,
- <vscale x 1 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv2i16(
- <vscale x 4 x i16>,
- <vscale x 2 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv2i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv2i16(
- <vscale x 4 x i16> %0,
- <vscale x 2 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv2i16(
- <vscale x 4 x i16>,
- <vscale x 2 x i16>,
- <vscale x 4 x i16>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv2i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv2i16(
- <vscale x 4 x i16> %0,
- <vscale x 2 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv4i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv4i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv4i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv4i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv4i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv4i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv8i16(
- <vscale x 4 x i16>,
- <vscale x 8 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv8i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v10, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv8i16(
- <vscale x 4 x i16> %0,
- <vscale x 8 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv8i16(
- <vscale x 4 x i16>,
- <vscale x 8 x i16>,
- <vscale x 4 x i16>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv8i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v10, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv8i16(
- <vscale x 4 x i16> %0,
- <vscale x 8 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv16i16(
- <vscale x 4 x i16>,
- <vscale x 16 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv16i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v12, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv16i16(
- <vscale x 4 x i16> %0,
- <vscale x 16 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv16i16(
- <vscale x 4 x i16>,
- <vscale x 16 x i16>,
- <vscale x 4 x i16>,
- <vscale x 16 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv16i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v12, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv16i16(
- <vscale x 4 x i16> %0,
- <vscale x 16 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 16 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv32i16(
- <vscale x 4 x i16>,
- <vscale x 32 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv32i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v16, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv32i16(
- <vscale x 4 x i16> %0,
- <vscale x 32 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv32i16(
- <vscale x 4 x i16>,
- <vscale x 32 x i16>,
- <vscale x 4 x i16>,
- <vscale x 32 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv32i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v16, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv32i16(
- <vscale x 4 x i16> %0,
- <vscale x 32 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 32 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv1i32(
- <vscale x 2 x i32>,
- <vscale x 1 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv1i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv1i32(
- <vscale x 2 x i32> %0,
- <vscale x 1 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv1i32(
- <vscale x 2 x i32>,
- <vscale x 1 x i32>,
- <vscale x 2 x i32>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv1i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv1i32(
- <vscale x 2 x i32> %0,
- <vscale x 1 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv2i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv2i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv2i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv2i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv4i32(
- <vscale x 2 x i32>,
- <vscale x 4 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv4i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v10, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv4i32(
- <vscale x 2 x i32> %0,
- <vscale x 4 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv4i32(
- <vscale x 2 x i32>,
- <vscale x 4 x i32>,
- <vscale x 2 x i32>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv4i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v10, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv4i32(
- <vscale x 2 x i32> %0,
- <vscale x 4 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv8i32(
- <vscale x 2 x i32>,
- <vscale x 8 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv8i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v12, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv8i32(
- <vscale x 2 x i32> %0,
- <vscale x 8 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv8i32(
- <vscale x 2 x i32>,
- <vscale x 8 x i32>,
- <vscale x 2 x i32>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv8i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v12, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv8i32(
- <vscale x 2 x i32> %0,
- <vscale x 8 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv16i32(
- <vscale x 2 x i32>,
- <vscale x 16 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv16i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v16, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv16i32(
- <vscale x 2 x i32> %0,
- <vscale x 16 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv16i32(
- <vscale x 2 x i32>,
- <vscale x 16 x i32>,
- <vscale x 2 x i32>,
- <vscale x 16 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv16i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v16, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv16i32(
- <vscale x 2 x i32> %0,
- <vscale x 16 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 16 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv1i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredmax_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv1i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv1i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- <vscale x 1 x i64> %2,
- i64 %3)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv1i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredmax_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv1i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv1i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv2i64(
- <vscale x 1 x i64>,
- <vscale x 2 x i64>,
- <vscale x 1 x i64>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredmax_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv2i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v10, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv2i64(
- <vscale x 1 x i64> %0,
- <vscale x 2 x i64> %1,
- <vscale x 1 x i64> %2,
- i64 %3)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv2i64(
- <vscale x 1 x i64>,
- <vscale x 2 x i64>,
- <vscale x 1 x i64>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredmax_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv2i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v10, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv2i64(
- <vscale x 1 x i64> %0,
- <vscale x 2 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv4i64(
- <vscale x 1 x i64>,
- <vscale x 4 x i64>,
- <vscale x 1 x i64>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredmax_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv4i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v12, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv4i64(
- <vscale x 1 x i64> %0,
- <vscale x 4 x i64> %1,
- <vscale x 1 x i64> %2,
- i64 %3)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv4i64(
- <vscale x 1 x i64>,
- <vscale x 4 x i64>,
- <vscale x 1 x i64>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredmax_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv4i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v12, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv4i64(
- <vscale x 1 x i64> %0,
- <vscale x 4 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv8i64(
- <vscale x 1 x i64>,
- <vscale x 8 x i64>,
- <vscale x 1 x i64>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredmax_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv8i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v16, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv8i64(
- <vscale x 1 x i64> %0,
- <vscale x 8 x i64> %1,
- <vscale x 1 x i64> %2,
- i64 %3)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv8i64(
- <vscale x 1 x i64>,
- <vscale x 8 x i64>,
- <vscale x 1 x i64>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredmax_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv8i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vredmax.vs v8, v16, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv8i64(
- <vscale x 1 x i64> %0,
- <vscale x 8 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i64> %a
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vredmax.ll
similarity index 90%
rename from llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll
rename to llvm/test/CodeGen/RISCV/rvv/vredmax.ll
index 745abee375d986..3808f2fcc2152a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vredmax.ll
@@ -1,13 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s
declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8(
<vscale x 8 x i8>,
<vscale x 1 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
@@ -18,7 +20,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 1 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -28,9 +30,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 8 x i8>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
@@ -42,7 +44,7 @@ entry:
<vscale x 1 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -51,9 +53,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8(
<vscale x 8 x i8>,
<vscale x 2 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
@@ -64,7 +66,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 2 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -74,9 +76,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 8 x i8>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
@@ -88,7 +90,7 @@ entry:
<vscale x 2 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -97,9 +99,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8(
<vscale x 8 x i8>,
<vscale x 4 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
@@ -110,7 +112,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 4 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -120,9 +122,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 8 x i8>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
@@ -134,7 +136,7 @@ entry:
<vscale x 4 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -143,9 +145,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
@@ -156,7 +158,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -166,9 +168,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
@@ -180,7 +182,7 @@ entry:
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -189,9 +191,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8(
<vscale x 8 x i8>,
<vscale x 16 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
@@ -202,7 +204,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 16 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -212,9 +214,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 8 x i8>,
<vscale x 16 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
@@ -226,7 +228,7 @@ entry:
<vscale x 16 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 16 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -235,9 +237,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8(
<vscale x 8 x i8>,
<vscale x 32 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
@@ -248,7 +250,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 32 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -258,9 +260,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 8 x i8>,
<vscale x 32 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
@@ -272,7 +274,7 @@ entry:
<vscale x 32 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 32 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -281,9 +283,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16(
<vscale x 4 x i16>,
<vscale x 1 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
@@ -294,7 +296,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 1 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -304,9 +306,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 4 x i16>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
@@ -318,7 +320,7 @@ entry:
<vscale x 1 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -327,9 +329,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv2i16(
<vscale x 4 x i16>,
<vscale x 2 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
@@ -340,7 +342,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 2 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -350,9 +352,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 4 x i16>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
@@ -364,7 +366,7 @@ entry:
<vscale x 2 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -373,9 +375,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
@@ -386,7 +388,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -396,9 +398,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
@@ -410,7 +412,7 @@ entry:
<vscale x 4 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -419,9 +421,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv8i16(
<vscale x 4 x i16>,
<vscale x 8 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
@@ -432,7 +434,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 8 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -442,9 +444,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 4 x i16>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
@@ -456,7 +458,7 @@ entry:
<vscale x 8 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -465,9 +467,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv16i16(
<vscale x 4 x i16>,
<vscale x 16 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
@@ -478,7 +480,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 16 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -488,9 +490,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 4 x i16>,
<vscale x 16 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
@@ -502,7 +504,7 @@ entry:
<vscale x 16 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 16 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -511,9 +513,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv32i16(
<vscale x 4 x i16>,
<vscale x 32 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
@@ -524,7 +526,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 32 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -534,9 +536,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 4 x i16>,
<vscale x 32 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
@@ -548,7 +550,7 @@ entry:
<vscale x 32 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 32 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -557,9 +559,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv1i32(
<vscale x 2 x i32>,
<vscale x 1 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
@@ -570,7 +572,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 1 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -580,9 +582,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 2 x i32>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
@@ -594,7 +596,7 @@ entry:
<vscale x 1 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -603,9 +605,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
@@ -616,7 +618,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -626,9 +628,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
@@ -640,7 +642,7 @@ entry:
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -649,9 +651,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv4i32(
<vscale x 2 x i32>,
<vscale x 4 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
@@ -662,7 +664,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 4 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -672,9 +674,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 2 x i32>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
@@ -686,7 +688,7 @@ entry:
<vscale x 4 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -695,9 +697,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv8i32(
<vscale x 2 x i32>,
<vscale x 8 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
@@ -708,7 +710,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 8 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -718,9 +720,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 2 x i32>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
@@ -732,7 +734,7 @@ entry:
<vscale x 8 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -741,9 +743,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv16i32(
<vscale x 2 x i32>,
<vscale x 16 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
@@ -754,7 +756,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 16 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -764,9 +766,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 2 x i32>,
<vscale x 16 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
@@ -778,7 +780,7 @@ entry:
<vscale x 16 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 16 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -787,9 +789,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i64>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredmax_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredmax_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
@@ -800,7 +802,7 @@ entry:
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
<vscale x 1 x i64> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 1 x i64> %a
}
@@ -810,9 +812,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredmax_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredmax_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
@@ -824,7 +826,7 @@ entry:
<vscale x 1 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i64> %a
}
@@ -833,9 +835,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv2i64(
<vscale x 1 x i64>,
<vscale x 2 x i64>,
<vscale x 1 x i64>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredmax_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredmax_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
@@ -846,7 +848,7 @@ entry:
<vscale x 1 x i64> %0,
<vscale x 2 x i64> %1,
<vscale x 1 x i64> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 1 x i64> %a
}
@@ -856,9 +858,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 1 x i64>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredmax_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredmax_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
@@ -870,7 +872,7 @@ entry:
<vscale x 2 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i64> %a
}
@@ -879,9 +881,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv4i64(
<vscale x 1 x i64>,
<vscale x 4 x i64>,
<vscale x 1 x i64>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredmax_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredmax_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
@@ -892,7 +894,7 @@ entry:
<vscale x 1 x i64> %0,
<vscale x 4 x i64> %1,
<vscale x 1 x i64> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 1 x i64> %a
}
@@ -902,9 +904,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 1 x i64>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredmax_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredmax_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
@@ -916,7 +918,7 @@ entry:
<vscale x 4 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i64> %a
}
@@ -925,9 +927,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv8i64(
<vscale x 1 x i64>,
<vscale x 8 x i64>,
<vscale x 1 x i64>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredmax_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredmax_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
@@ -938,7 +940,7 @@ entry:
<vscale x 1 x i64> %0,
<vscale x 8 x i64> %1,
<vscale x 1 x i64> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 1 x i64> %a
}
@@ -948,9 +950,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 1 x i64>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredmax_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredmax_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
@@ -962,7 +964,7 @@ entry:
<vscale x 8 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i64> %a
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll
deleted file mode 100644
index 22cc5ef74b4bfb..00000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll
+++ /dev/null
@@ -1,968 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
-declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8(
- <vscale x 8 x i8>,
- <vscale x 1 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv1i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8(
- <vscale x 8 x i8> %0,
- <vscale x 1 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv1i8(
- <vscale x 8 x i8>,
- <vscale x 1 x i8>,
- <vscale x 8 x i8>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv1i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv1i8(
- <vscale x 8 x i8> %0,
- <vscale x 1 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8(
- <vscale x 8 x i8>,
- <vscale x 2 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv2i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8(
- <vscale x 8 x i8> %0,
- <vscale x 2 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv2i8(
- <vscale x 8 x i8>,
- <vscale x 2 x i8>,
- <vscale x 8 x i8>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv2i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv2i8(
- <vscale x 8 x i8> %0,
- <vscale x 2 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8(
- <vscale x 8 x i8>,
- <vscale x 4 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv4i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8(
- <vscale x 8 x i8> %0,
- <vscale x 4 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv4i8(
- <vscale x 8 x i8>,
- <vscale x 4 x i8>,
- <vscale x 8 x i8>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv4i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv4i8(
- <vscale x 8 x i8> %0,
- <vscale x 4 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv8i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv8i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv8i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv8i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8(
- <vscale x 8 x i8>,
- <vscale x 16 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv16i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v10, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8(
- <vscale x 8 x i8> %0,
- <vscale x 16 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv16i8(
- <vscale x 8 x i8>,
- <vscale x 16 x i8>,
- <vscale x 8 x i8>,
- <vscale x 16 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv16i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v10, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv16i8(
- <vscale x 8 x i8> %0,
- <vscale x 16 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 16 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8(
- <vscale x 8 x i8>,
- <vscale x 32 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv32i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v12, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8(
- <vscale x 8 x i8> %0,
- <vscale x 32 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv32i8(
- <vscale x 8 x i8>,
- <vscale x 32 x i8>,
- <vscale x 8 x i8>,
- <vscale x 32 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv32i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v12, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv32i8(
- <vscale x 8 x i8> %0,
- <vscale x 32 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 32 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16(
- <vscale x 4 x i16>,
- <vscale x 1 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv1i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16(
- <vscale x 4 x i16> %0,
- <vscale x 1 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv1i16(
- <vscale x 4 x i16>,
- <vscale x 1 x i16>,
- <vscale x 4 x i16>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv1i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv1i16(
- <vscale x 4 x i16> %0,
- <vscale x 1 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv2i16(
- <vscale x 4 x i16>,
- <vscale x 2 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv2i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv2i16(
- <vscale x 4 x i16> %0,
- <vscale x 2 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv2i16(
- <vscale x 4 x i16>,
- <vscale x 2 x i16>,
- <vscale x 4 x i16>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv2i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv2i16(
- <vscale x 4 x i16> %0,
- <vscale x 2 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv4i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv4i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv4i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv4i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv4i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv4i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv8i16(
- <vscale x 4 x i16>,
- <vscale x 8 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv8i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v10, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv8i16(
- <vscale x 4 x i16> %0,
- <vscale x 8 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv8i16(
- <vscale x 4 x i16>,
- <vscale x 8 x i16>,
- <vscale x 4 x i16>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv8i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v10, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv8i16(
- <vscale x 4 x i16> %0,
- <vscale x 8 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv16i16(
- <vscale x 4 x i16>,
- <vscale x 16 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv16i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v12, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv16i16(
- <vscale x 4 x i16> %0,
- <vscale x 16 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv16i16(
- <vscale x 4 x i16>,
- <vscale x 16 x i16>,
- <vscale x 4 x i16>,
- <vscale x 16 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv16i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v12, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv16i16(
- <vscale x 4 x i16> %0,
- <vscale x 16 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 16 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv32i16(
- <vscale x 4 x i16>,
- <vscale x 32 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv32i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v16, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv32i16(
- <vscale x 4 x i16> %0,
- <vscale x 32 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv32i16(
- <vscale x 4 x i16>,
- <vscale x 32 x i16>,
- <vscale x 4 x i16>,
- <vscale x 32 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv32i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v16, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv32i16(
- <vscale x 4 x i16> %0,
- <vscale x 32 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 32 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv1i32(
- <vscale x 2 x i32>,
- <vscale x 1 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv1i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv1i32(
- <vscale x 2 x i32> %0,
- <vscale x 1 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv1i32(
- <vscale x 2 x i32>,
- <vscale x 1 x i32>,
- <vscale x 2 x i32>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv1i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv1i32(
- <vscale x 2 x i32> %0,
- <vscale x 1 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv2i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv2i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv2i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv2i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv4i32(
- <vscale x 2 x i32>,
- <vscale x 4 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv4i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v10, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv4i32(
- <vscale x 2 x i32> %0,
- <vscale x 4 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv4i32(
- <vscale x 2 x i32>,
- <vscale x 4 x i32>,
- <vscale x 2 x i32>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv4i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v10, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv4i32(
- <vscale x 2 x i32> %0,
- <vscale x 4 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv8i32(
- <vscale x 2 x i32>,
- <vscale x 8 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv8i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v12, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv8i32(
- <vscale x 2 x i32> %0,
- <vscale x 8 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv8i32(
- <vscale x 2 x i32>,
- <vscale x 8 x i32>,
- <vscale x 2 x i32>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv8i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v12, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv8i32(
- <vscale x 2 x i32> %0,
- <vscale x 8 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv16i32(
- <vscale x 2 x i32>,
- <vscale x 16 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv16i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v16, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv16i32(
- <vscale x 2 x i32> %0,
- <vscale x 16 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv16i32(
- <vscale x 2 x i32>,
- <vscale x 16 x i32>,
- <vscale x 2 x i32>,
- <vscale x 16 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv16i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v16, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv16i32(
- <vscale x 2 x i32> %0,
- <vscale x 16 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 16 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv1i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredmaxu_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv1i64_nxv1i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv1i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- <vscale x 1 x i64> %2,
- i64 %3)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv1i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredmaxu_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv1i64_nxv1i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv1i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv2i64(
- <vscale x 1 x i64>,
- <vscale x 2 x i64>,
- <vscale x 1 x i64>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredmaxu_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv1i64_nxv2i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v10, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv2i64(
- <vscale x 1 x i64> %0,
- <vscale x 2 x i64> %1,
- <vscale x 1 x i64> %2,
- i64 %3)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv2i64(
- <vscale x 1 x i64>,
- <vscale x 2 x i64>,
- <vscale x 1 x i64>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredmaxu_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv1i64_nxv2i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v10, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv2i64(
- <vscale x 1 x i64> %0,
- <vscale x 2 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv4i64(
- <vscale x 1 x i64>,
- <vscale x 4 x i64>,
- <vscale x 1 x i64>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredmaxu_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv1i64_nxv4i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v12, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv4i64(
- <vscale x 1 x i64> %0,
- <vscale x 4 x i64> %1,
- <vscale x 1 x i64> %2,
- i64 %3)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv4i64(
- <vscale x 1 x i64>,
- <vscale x 4 x i64>,
- <vscale x 1 x i64>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredmaxu_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv1i64_nxv4i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v12, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv4i64(
- <vscale x 1 x i64> %0,
- <vscale x 4 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv8i64(
- <vscale x 1 x i64>,
- <vscale x 8 x i64>,
- <vscale x 1 x i64>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredmaxu_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv1i64_nxv8i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v16, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv8i64(
- <vscale x 1 x i64> %0,
- <vscale x 8 x i64> %1,
- <vscale x 1 x i64> %2,
- i64 %3)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv8i64(
- <vscale x 1 x i64>,
- <vscale x 8 x i64>,
- <vscale x 1 x i64>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredmaxu_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv1i64_nxv8i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vredmaxu.vs v8, v16, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv8i64(
- <vscale x 1 x i64> %0,
- <vscale x 8 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i64> %a
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vredmaxu.ll
similarity index 90%
rename from llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll
rename to llvm/test/CodeGen/RISCV/rvv/vredmaxu.ll
index 01be00d6790ec9..ad0eb6611bc833 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vredmaxu.ll
@@ -1,13 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s
declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8(
<vscale x 8 x i8>,
<vscale x 1 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
@@ -18,7 +20,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 1 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -28,9 +30,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 8 x i8>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
@@ -42,7 +44,7 @@ entry:
<vscale x 1 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -51,9 +53,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8(
<vscale x 8 x i8>,
<vscale x 2 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
@@ -64,7 +66,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 2 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -74,9 +76,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 8 x i8>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
@@ -88,7 +90,7 @@ entry:
<vscale x 2 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -97,9 +99,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8(
<vscale x 8 x i8>,
<vscale x 4 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
@@ -110,7 +112,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 4 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -120,9 +122,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 8 x i8>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
@@ -134,7 +136,7 @@ entry:
<vscale x 4 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -143,9 +145,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
@@ -156,7 +158,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -166,9 +168,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
@@ -180,7 +182,7 @@ entry:
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -189,9 +191,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8(
<vscale x 8 x i8>,
<vscale x 16 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
@@ -202,7 +204,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 16 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -212,9 +214,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 8 x i8>,
<vscale x 16 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
@@ -226,7 +228,7 @@ entry:
<vscale x 16 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 16 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -235,9 +237,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8(
<vscale x 8 x i8>,
<vscale x 32 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
@@ -248,7 +250,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 32 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -258,9 +260,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 8 x i8>,
<vscale x 32 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
@@ -272,7 +274,7 @@ entry:
<vscale x 32 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 32 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -281,9 +283,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16(
<vscale x 4 x i16>,
<vscale x 1 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
@@ -294,7 +296,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 1 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -304,9 +306,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 4 x i16>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
@@ -318,7 +320,7 @@ entry:
<vscale x 1 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -327,9 +329,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv2i16(
<vscale x 4 x i16>,
<vscale x 2 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
@@ -340,7 +342,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 2 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -350,9 +352,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 4 x i16>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
@@ -364,7 +366,7 @@ entry:
<vscale x 2 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -373,9 +375,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
@@ -386,7 +388,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -396,9 +398,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
@@ -410,7 +412,7 @@ entry:
<vscale x 4 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -419,9 +421,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv8i16(
<vscale x 4 x i16>,
<vscale x 8 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
@@ -432,7 +434,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 8 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -442,9 +444,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 4 x i16>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
@@ -456,7 +458,7 @@ entry:
<vscale x 8 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -465,9 +467,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv16i16(
<vscale x 4 x i16>,
<vscale x 16 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
@@ -478,7 +480,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 16 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -488,9 +490,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 4 x i16>,
<vscale x 16 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
@@ -502,7 +504,7 @@ entry:
<vscale x 16 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 16 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -511,9 +513,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv32i16(
<vscale x 4 x i16>,
<vscale x 32 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
@@ -524,7 +526,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 32 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -534,9 +536,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 4 x i16>,
<vscale x 32 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
@@ -548,7 +550,7 @@ entry:
<vscale x 32 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 32 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -557,9 +559,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv1i32(
<vscale x 2 x i32>,
<vscale x 1 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
@@ -570,7 +572,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 1 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -580,9 +582,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 2 x i32>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
@@ -594,7 +596,7 @@ entry:
<vscale x 1 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -603,9 +605,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
@@ -616,7 +618,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -626,9 +628,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
@@ -640,7 +642,7 @@ entry:
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -649,9 +651,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv4i32(
<vscale x 2 x i32>,
<vscale x 4 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
@@ -662,7 +664,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 4 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -672,9 +674,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 2 x i32>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
@@ -686,7 +688,7 @@ entry:
<vscale x 4 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -695,9 +697,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv8i32(
<vscale x 2 x i32>,
<vscale x 8 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
@@ -708,7 +710,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 8 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -718,9 +720,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 2 x i32>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
@@ -732,7 +734,7 @@ entry:
<vscale x 8 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -741,9 +743,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv16i32(
<vscale x 2 x i32>,
<vscale x 16 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
@@ -754,7 +756,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 16 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -764,9 +766,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 2 x i32>,
<vscale x 16 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
@@ -778,7 +780,7 @@ entry:
<vscale x 16 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 16 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -787,9 +789,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i64>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredmaxu_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredmaxu_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
@@ -800,7 +802,7 @@ entry:
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
<vscale x 1 x i64> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 1 x i64> %a
}
@@ -810,9 +812,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredmaxu_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredmaxu_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
@@ -824,7 +826,7 @@ entry:
<vscale x 1 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i64> %a
}
@@ -833,9 +835,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv2i64(
<vscale x 1 x i64>,
<vscale x 2 x i64>,
<vscale x 1 x i64>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredmaxu_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredmaxu_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
@@ -846,7 +848,7 @@ entry:
<vscale x 1 x i64> %0,
<vscale x 2 x i64> %1,
<vscale x 1 x i64> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 1 x i64> %a
}
@@ -856,9 +858,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 1 x i64>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredmaxu_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredmaxu_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
@@ -870,7 +872,7 @@ entry:
<vscale x 2 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i64> %a
}
@@ -879,9 +881,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv4i64(
<vscale x 1 x i64>,
<vscale x 4 x i64>,
<vscale x 1 x i64>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredmaxu_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredmaxu_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
@@ -892,7 +894,7 @@ entry:
<vscale x 1 x i64> %0,
<vscale x 4 x i64> %1,
<vscale x 1 x i64> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 1 x i64> %a
}
@@ -902,9 +904,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 1 x i64>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredmaxu_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredmaxu_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
@@ -916,7 +918,7 @@ entry:
<vscale x 4 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i64> %a
}
@@ -925,9 +927,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv8i64(
<vscale x 1 x i64>,
<vscale x 8 x i64>,
<vscale x 1 x i64>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredmaxu_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredmaxu_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
@@ -938,7 +940,7 @@ entry:
<vscale x 1 x i64> %0,
<vscale x 8 x i64> %1,
<vscale x 1 x i64> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 1 x i64> %a
}
@@ -948,9 +950,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 1 x i64>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredmaxu_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredmaxu_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
@@ -962,7 +964,7 @@ entry:
<vscale x 8 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i64> %a
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll
deleted file mode 100644
index e4d6180378f507..00000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll
+++ /dev/null
@@ -1,968 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
-declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8(
- <vscale x 8 x i8>,
- <vscale x 1 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv1i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8(
- <vscale x 8 x i8> %0,
- <vscale x 1 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv1i8(
- <vscale x 8 x i8>,
- <vscale x 1 x i8>,
- <vscale x 8 x i8>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv1i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv1i8(
- <vscale x 8 x i8> %0,
- <vscale x 1 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8(
- <vscale x 8 x i8>,
- <vscale x 2 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv2i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8(
- <vscale x 8 x i8> %0,
- <vscale x 2 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv2i8(
- <vscale x 8 x i8>,
- <vscale x 2 x i8>,
- <vscale x 8 x i8>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv2i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv2i8(
- <vscale x 8 x i8> %0,
- <vscale x 2 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8(
- <vscale x 8 x i8>,
- <vscale x 4 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv4i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8(
- <vscale x 8 x i8> %0,
- <vscale x 4 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv4i8(
- <vscale x 8 x i8>,
- <vscale x 4 x i8>,
- <vscale x 8 x i8>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv4i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv4i8(
- <vscale x 8 x i8> %0,
- <vscale x 4 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv8i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv8i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv8i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv8i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8(
- <vscale x 8 x i8>,
- <vscale x 16 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv16i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v10, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8(
- <vscale x 8 x i8> %0,
- <vscale x 16 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv16i8(
- <vscale x 8 x i8>,
- <vscale x 16 x i8>,
- <vscale x 8 x i8>,
- <vscale x 16 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv16i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v10, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv16i8(
- <vscale x 8 x i8> %0,
- <vscale x 16 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 16 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8(
- <vscale x 8 x i8>,
- <vscale x 32 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv32i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v12, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8(
- <vscale x 8 x i8> %0,
- <vscale x 32 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv32i8(
- <vscale x 8 x i8>,
- <vscale x 32 x i8>,
- <vscale x 8 x i8>,
- <vscale x 32 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv32i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v12, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv32i8(
- <vscale x 8 x i8> %0,
- <vscale x 32 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 32 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16(
- <vscale x 4 x i16>,
- <vscale x 1 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv1i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16(
- <vscale x 4 x i16> %0,
- <vscale x 1 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv1i16(
- <vscale x 4 x i16>,
- <vscale x 1 x i16>,
- <vscale x 4 x i16>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv1i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv1i16(
- <vscale x 4 x i16> %0,
- <vscale x 1 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv2i16(
- <vscale x 4 x i16>,
- <vscale x 2 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv2i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv2i16(
- <vscale x 4 x i16> %0,
- <vscale x 2 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv2i16(
- <vscale x 4 x i16>,
- <vscale x 2 x i16>,
- <vscale x 4 x i16>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv2i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv2i16(
- <vscale x 4 x i16> %0,
- <vscale x 2 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv4i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv4i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv4i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv4i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv4i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv4i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv8i16(
- <vscale x 4 x i16>,
- <vscale x 8 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv8i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v10, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv8i16(
- <vscale x 4 x i16> %0,
- <vscale x 8 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv8i16(
- <vscale x 4 x i16>,
- <vscale x 8 x i16>,
- <vscale x 4 x i16>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv8i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v10, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv8i16(
- <vscale x 4 x i16> %0,
- <vscale x 8 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv16i16(
- <vscale x 4 x i16>,
- <vscale x 16 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv16i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v12, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv16i16(
- <vscale x 4 x i16> %0,
- <vscale x 16 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv16i16(
- <vscale x 4 x i16>,
- <vscale x 16 x i16>,
- <vscale x 4 x i16>,
- <vscale x 16 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv16i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v12, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv16i16(
- <vscale x 4 x i16> %0,
- <vscale x 16 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 16 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv32i16(
- <vscale x 4 x i16>,
- <vscale x 32 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv32i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v16, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv32i16(
- <vscale x 4 x i16> %0,
- <vscale x 32 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv32i16(
- <vscale x 4 x i16>,
- <vscale x 32 x i16>,
- <vscale x 4 x i16>,
- <vscale x 32 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv32i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v16, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv32i16(
- <vscale x 4 x i16> %0,
- <vscale x 32 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 32 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv1i32(
- <vscale x 2 x i32>,
- <vscale x 1 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv1i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv1i32(
- <vscale x 2 x i32> %0,
- <vscale x 1 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv1i32(
- <vscale x 2 x i32>,
- <vscale x 1 x i32>,
- <vscale x 2 x i32>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv1i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv1i32(
- <vscale x 2 x i32> %0,
- <vscale x 1 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv2i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv2i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv2i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv2i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv4i32(
- <vscale x 2 x i32>,
- <vscale x 4 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv4i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v10, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv4i32(
- <vscale x 2 x i32> %0,
- <vscale x 4 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv4i32(
- <vscale x 2 x i32>,
- <vscale x 4 x i32>,
- <vscale x 2 x i32>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv4i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v10, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv4i32(
- <vscale x 2 x i32> %0,
- <vscale x 4 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv8i32(
- <vscale x 2 x i32>,
- <vscale x 8 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv8i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v12, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv8i32(
- <vscale x 2 x i32> %0,
- <vscale x 8 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv8i32(
- <vscale x 2 x i32>,
- <vscale x 8 x i32>,
- <vscale x 2 x i32>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv8i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v12, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv8i32(
- <vscale x 2 x i32> %0,
- <vscale x 8 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv16i32(
- <vscale x 2 x i32>,
- <vscale x 16 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv16i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v16, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv16i32(
- <vscale x 2 x i32> %0,
- <vscale x 16 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv16i32(
- <vscale x 2 x i32>,
- <vscale x 16 x i32>,
- <vscale x 2 x i32>,
- <vscale x 16 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv16i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v16, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv16i32(
- <vscale x 2 x i32> %0,
- <vscale x 16 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 16 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv1i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredmin_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_vs_nxv1i64_nxv1i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv1i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- <vscale x 1 x i64> %2,
- i64 %3)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv1i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredmin_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv1i64_nxv1i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv1i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv2i64(
- <vscale x 1 x i64>,
- <vscale x 2 x i64>,
- <vscale x 1 x i64>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredmin_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_vs_nxv1i64_nxv2i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v10, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv2i64(
- <vscale x 1 x i64> %0,
- <vscale x 2 x i64> %1,
- <vscale x 1 x i64> %2,
- i64 %3)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv2i64(
- <vscale x 1 x i64>,
- <vscale x 2 x i64>,
- <vscale x 1 x i64>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredmin_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv1i64_nxv2i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v10, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv2i64(
- <vscale x 1 x i64> %0,
- <vscale x 2 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv4i64(
- <vscale x 1 x i64>,
- <vscale x 4 x i64>,
- <vscale x 1 x i64>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredmin_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_vs_nxv1i64_nxv4i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v12, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv4i64(
- <vscale x 1 x i64> %0,
- <vscale x 4 x i64> %1,
- <vscale x 1 x i64> %2,
- i64 %3)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv4i64(
- <vscale x 1 x i64>,
- <vscale x 4 x i64>,
- <vscale x 1 x i64>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredmin_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv1i64_nxv4i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v12, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv4i64(
- <vscale x 1 x i64> %0,
- <vscale x 4 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv8i64(
- <vscale x 1 x i64>,
- <vscale x 8 x i64>,
- <vscale x 1 x i64>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredmin_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_vs_nxv1i64_nxv8i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v16, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv8i64(
- <vscale x 1 x i64> %0,
- <vscale x 8 x i64> %1,
- <vscale x 1 x i64> %2,
- i64 %3)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv8i64(
- <vscale x 1 x i64>,
- <vscale x 8 x i64>,
- <vscale x 1 x i64>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredmin_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv1i64_nxv8i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vredmin.vs v8, v16, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv8i64(
- <vscale x 1 x i64> %0,
- <vscale x 8 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i64> %a
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vredmin.ll
similarity index 90%
rename from llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll
rename to llvm/test/CodeGen/RISCV/rvv/vredmin.ll
index 594916ac7e329e..04c67fa75ed6fd 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vredmin.ll
@@ -1,13 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s
declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8(
<vscale x 8 x i8>,
<vscale x 1 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
@@ -18,7 +20,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 1 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -28,9 +30,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 8 x i8>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
@@ -42,7 +44,7 @@ entry:
<vscale x 1 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -51,9 +53,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8(
<vscale x 8 x i8>,
<vscale x 2 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
@@ -64,7 +66,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 2 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -74,9 +76,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 8 x i8>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
@@ -88,7 +90,7 @@ entry:
<vscale x 2 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -97,9 +99,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8(
<vscale x 8 x i8>,
<vscale x 4 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
@@ -110,7 +112,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 4 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -120,9 +122,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 8 x i8>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
@@ -134,7 +136,7 @@ entry:
<vscale x 4 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -143,9 +145,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
@@ -156,7 +158,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -166,9 +168,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
@@ -180,7 +182,7 @@ entry:
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -189,9 +191,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8(
<vscale x 8 x i8>,
<vscale x 16 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
@@ -202,7 +204,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 16 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -212,9 +214,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 8 x i8>,
<vscale x 16 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
@@ -226,7 +228,7 @@ entry:
<vscale x 16 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 16 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -235,9 +237,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8(
<vscale x 8 x i8>,
<vscale x 32 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
@@ -248,7 +250,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 32 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -258,9 +260,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 8 x i8>,
<vscale x 32 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
@@ -272,7 +274,7 @@ entry:
<vscale x 32 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 32 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -281,9 +283,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16(
<vscale x 4 x i16>,
<vscale x 1 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
@@ -294,7 +296,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 1 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -304,9 +306,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 4 x i16>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
@@ -318,7 +320,7 @@ entry:
<vscale x 1 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -327,9 +329,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv2i16(
<vscale x 4 x i16>,
<vscale x 2 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
@@ -340,7 +342,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 2 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -350,9 +352,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 4 x i16>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
@@ -364,7 +366,7 @@ entry:
<vscale x 2 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -373,9 +375,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
@@ -386,7 +388,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -396,9 +398,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
@@ -410,7 +412,7 @@ entry:
<vscale x 4 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -419,9 +421,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv8i16(
<vscale x 4 x i16>,
<vscale x 8 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
@@ -432,7 +434,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 8 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -442,9 +444,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 4 x i16>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
@@ -456,7 +458,7 @@ entry:
<vscale x 8 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -465,9 +467,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv16i16(
<vscale x 4 x i16>,
<vscale x 16 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
@@ -478,7 +480,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 16 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -488,9 +490,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 4 x i16>,
<vscale x 16 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
@@ -502,7 +504,7 @@ entry:
<vscale x 16 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 16 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -511,9 +513,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv32i16(
<vscale x 4 x i16>,
<vscale x 32 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
@@ -524,7 +526,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 32 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -534,9 +536,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 4 x i16>,
<vscale x 32 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
@@ -548,7 +550,7 @@ entry:
<vscale x 32 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 32 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -557,9 +559,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv1i32(
<vscale x 2 x i32>,
<vscale x 1 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
@@ -570,7 +572,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 1 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -580,9 +582,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 2 x i32>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
@@ -594,7 +596,7 @@ entry:
<vscale x 1 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -603,9 +605,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
@@ -616,7 +618,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -626,9 +628,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
@@ -640,7 +642,7 @@ entry:
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -649,9 +651,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv4i32(
<vscale x 2 x i32>,
<vscale x 4 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
@@ -662,7 +664,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 4 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -672,9 +674,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 2 x i32>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
@@ -686,7 +688,7 @@ entry:
<vscale x 4 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -695,9 +697,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv8i32(
<vscale x 2 x i32>,
<vscale x 8 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
@@ -708,7 +710,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 8 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -718,9 +720,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 2 x i32>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
@@ -732,7 +734,7 @@ entry:
<vscale x 8 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -741,9 +743,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv16i32(
<vscale x 2 x i32>,
<vscale x 16 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
@@ -754,7 +756,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 16 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -764,9 +766,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 2 x i32>,
<vscale x 16 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
@@ -778,7 +780,7 @@ entry:
<vscale x 16 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 16 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -787,9 +789,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i64>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredmin_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredmin_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
@@ -800,7 +802,7 @@ entry:
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
<vscale x 1 x i64> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 1 x i64> %a
}
@@ -810,9 +812,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredmin_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredmin_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
@@ -824,7 +826,7 @@ entry:
<vscale x 1 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i64> %a
}
@@ -833,9 +835,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv2i64(
<vscale x 1 x i64>,
<vscale x 2 x i64>,
<vscale x 1 x i64>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredmin_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredmin_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
@@ -846,7 +848,7 @@ entry:
<vscale x 1 x i64> %0,
<vscale x 2 x i64> %1,
<vscale x 1 x i64> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 1 x i64> %a
}
@@ -856,9 +858,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 1 x i64>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredmin_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredmin_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
@@ -870,7 +872,7 @@ entry:
<vscale x 2 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i64> %a
}
@@ -879,9 +881,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv4i64(
<vscale x 1 x i64>,
<vscale x 4 x i64>,
<vscale x 1 x i64>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredmin_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredmin_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
@@ -892,7 +894,7 @@ entry:
<vscale x 1 x i64> %0,
<vscale x 4 x i64> %1,
<vscale x 1 x i64> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 1 x i64> %a
}
@@ -902,9 +904,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 1 x i64>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredmin_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredmin_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
@@ -916,7 +918,7 @@ entry:
<vscale x 4 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i64> %a
}
@@ -925,9 +927,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv8i64(
<vscale x 1 x i64>,
<vscale x 8 x i64>,
<vscale x 1 x i64>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredmin_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredmin_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
@@ -938,7 +940,7 @@ entry:
<vscale x 1 x i64> %0,
<vscale x 8 x i64> %1,
<vscale x 1 x i64> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 1 x i64> %a
}
@@ -948,9 +950,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 1 x i64>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredmin_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredmin_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
@@ -962,7 +964,7 @@ entry:
<vscale x 8 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i64> %a
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll
deleted file mode 100644
index 506127ba221d10..00000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll
+++ /dev/null
@@ -1,968 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
-declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8(
- <vscale x 8 x i8>,
- <vscale x 1 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv1i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8(
- <vscale x 8 x i8> %0,
- <vscale x 1 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv1i8(
- <vscale x 8 x i8>,
- <vscale x 1 x i8>,
- <vscale x 8 x i8>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv1i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv1i8(
- <vscale x 8 x i8> %0,
- <vscale x 1 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8(
- <vscale x 8 x i8>,
- <vscale x 2 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv2i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8(
- <vscale x 8 x i8> %0,
- <vscale x 2 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv2i8(
- <vscale x 8 x i8>,
- <vscale x 2 x i8>,
- <vscale x 8 x i8>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv2i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv2i8(
- <vscale x 8 x i8> %0,
- <vscale x 2 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8(
- <vscale x 8 x i8>,
- <vscale x 4 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv4i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8(
- <vscale x 8 x i8> %0,
- <vscale x 4 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv4i8(
- <vscale x 8 x i8>,
- <vscale x 4 x i8>,
- <vscale x 8 x i8>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv4i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv4i8(
- <vscale x 8 x i8> %0,
- <vscale x 4 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv8i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv8i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv8i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv8i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8(
- <vscale x 8 x i8>,
- <vscale x 16 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv16i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v10, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8(
- <vscale x 8 x i8> %0,
- <vscale x 16 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv16i8(
- <vscale x 8 x i8>,
- <vscale x 16 x i8>,
- <vscale x 8 x i8>,
- <vscale x 16 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv16i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v10, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv16i8(
- <vscale x 8 x i8> %0,
- <vscale x 16 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 16 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8(
- <vscale x 8 x i8>,
- <vscale x 32 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv32i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v12, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8(
- <vscale x 8 x i8> %0,
- <vscale x 32 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv32i8(
- <vscale x 8 x i8>,
- <vscale x 32 x i8>,
- <vscale x 8 x i8>,
- <vscale x 32 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv32i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v12, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv32i8(
- <vscale x 8 x i8> %0,
- <vscale x 32 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 32 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16(
- <vscale x 4 x i16>,
- <vscale x 1 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv1i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16(
- <vscale x 4 x i16> %0,
- <vscale x 1 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv1i16(
- <vscale x 4 x i16>,
- <vscale x 1 x i16>,
- <vscale x 4 x i16>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv1i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv1i16(
- <vscale x 4 x i16> %0,
- <vscale x 1 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv2i16(
- <vscale x 4 x i16>,
- <vscale x 2 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv2i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv2i16(
- <vscale x 4 x i16> %0,
- <vscale x 2 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv2i16(
- <vscale x 4 x i16>,
- <vscale x 2 x i16>,
- <vscale x 4 x i16>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv2i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv2i16(
- <vscale x 4 x i16> %0,
- <vscale x 2 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv4i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv4i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv4i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv4i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv4i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv4i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv8i16(
- <vscale x 4 x i16>,
- <vscale x 8 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv8i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v10, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv8i16(
- <vscale x 4 x i16> %0,
- <vscale x 8 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv8i16(
- <vscale x 4 x i16>,
- <vscale x 8 x i16>,
- <vscale x 4 x i16>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv8i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v10, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv8i16(
- <vscale x 4 x i16> %0,
- <vscale x 8 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv16i16(
- <vscale x 4 x i16>,
- <vscale x 16 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv16i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v12, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv16i16(
- <vscale x 4 x i16> %0,
- <vscale x 16 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv16i16(
- <vscale x 4 x i16>,
- <vscale x 16 x i16>,
- <vscale x 4 x i16>,
- <vscale x 16 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv16i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v12, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv16i16(
- <vscale x 4 x i16> %0,
- <vscale x 16 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 16 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv32i16(
- <vscale x 4 x i16>,
- <vscale x 32 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv32i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v16, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv32i16(
- <vscale x 4 x i16> %0,
- <vscale x 32 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv32i16(
- <vscale x 4 x i16>,
- <vscale x 32 x i16>,
- <vscale x 4 x i16>,
- <vscale x 32 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv32i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v16, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv32i16(
- <vscale x 4 x i16> %0,
- <vscale x 32 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 32 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv1i32(
- <vscale x 2 x i32>,
- <vscale x 1 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv1i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv1i32(
- <vscale x 2 x i32> %0,
- <vscale x 1 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv1i32(
- <vscale x 2 x i32>,
- <vscale x 1 x i32>,
- <vscale x 2 x i32>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv1i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv1i32(
- <vscale x 2 x i32> %0,
- <vscale x 1 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv2i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv2i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv2i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv2i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv4i32(
- <vscale x 2 x i32>,
- <vscale x 4 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv4i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v10, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv4i32(
- <vscale x 2 x i32> %0,
- <vscale x 4 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv4i32(
- <vscale x 2 x i32>,
- <vscale x 4 x i32>,
- <vscale x 2 x i32>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv4i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v10, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv4i32(
- <vscale x 2 x i32> %0,
- <vscale x 4 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv8i32(
- <vscale x 2 x i32>,
- <vscale x 8 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv8i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v12, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv8i32(
- <vscale x 2 x i32> %0,
- <vscale x 8 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv8i32(
- <vscale x 2 x i32>,
- <vscale x 8 x i32>,
- <vscale x 2 x i32>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv8i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v12, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv8i32(
- <vscale x 2 x i32> %0,
- <vscale x 8 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv16i32(
- <vscale x 2 x i32>,
- <vscale x 16 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv16i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v16, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv16i32(
- <vscale x 2 x i32> %0,
- <vscale x 16 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv16i32(
- <vscale x 2 x i32>,
- <vscale x 16 x i32>,
- <vscale x 2 x i32>,
- <vscale x 16 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv16i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v16, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv16i32(
- <vscale x 2 x i32> %0,
- <vscale x 16 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 16 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv1i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredminu_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_vs_nxv1i64_nxv1i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv1i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- <vscale x 1 x i64> %2,
- i64 %3)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv1i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredminu_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv1i64_nxv1i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv1i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv2i64(
- <vscale x 1 x i64>,
- <vscale x 2 x i64>,
- <vscale x 1 x i64>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredminu_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_vs_nxv1i64_nxv2i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v10, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv2i64(
- <vscale x 1 x i64> %0,
- <vscale x 2 x i64> %1,
- <vscale x 1 x i64> %2,
- i64 %3)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv2i64(
- <vscale x 1 x i64>,
- <vscale x 2 x i64>,
- <vscale x 1 x i64>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredminu_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv1i64_nxv2i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v10, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv2i64(
- <vscale x 1 x i64> %0,
- <vscale x 2 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv4i64(
- <vscale x 1 x i64>,
- <vscale x 4 x i64>,
- <vscale x 1 x i64>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredminu_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_vs_nxv1i64_nxv4i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v12, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv4i64(
- <vscale x 1 x i64> %0,
- <vscale x 4 x i64> %1,
- <vscale x 1 x i64> %2,
- i64 %3)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv4i64(
- <vscale x 1 x i64>,
- <vscale x 4 x i64>,
- <vscale x 1 x i64>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredminu_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv1i64_nxv4i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v12, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv4i64(
- <vscale x 1 x i64> %0,
- <vscale x 4 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv8i64(
- <vscale x 1 x i64>,
- <vscale x 8 x i64>,
- <vscale x 1 x i64>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredminu_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_vs_nxv1i64_nxv8i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v16, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv8i64(
- <vscale x 1 x i64> %0,
- <vscale x 8 x i64> %1,
- <vscale x 1 x i64> %2,
- i64 %3)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv8i64(
- <vscale x 1 x i64>,
- <vscale x 8 x i64>,
- <vscale x 1 x i64>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredminu_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv1i64_nxv8i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vredminu.vs v8, v16, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv8i64(
- <vscale x 1 x i64> %0,
- <vscale x 8 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i64> %a
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vredminu.ll
similarity index 90%
rename from llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll
rename to llvm/test/CodeGen/RISCV/rvv/vredminu.ll
index e6b4d73f0178eb..9c02373e769f77 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vredminu.ll
@@ -1,13 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s
declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8(
<vscale x 8 x i8>,
<vscale x 1 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
@@ -18,7 +20,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 1 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -28,9 +30,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 8 x i8>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
@@ -42,7 +44,7 @@ entry:
<vscale x 1 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -51,9 +53,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8(
<vscale x 8 x i8>,
<vscale x 2 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
@@ -64,7 +66,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 2 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -74,9 +76,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 8 x i8>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
@@ -88,7 +90,7 @@ entry:
<vscale x 2 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -97,9 +99,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8(
<vscale x 8 x i8>,
<vscale x 4 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
@@ -110,7 +112,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 4 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -120,9 +122,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 8 x i8>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
@@ -134,7 +136,7 @@ entry:
<vscale x 4 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -143,9 +145,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
@@ -156,7 +158,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -166,9 +168,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
@@ -180,7 +182,7 @@ entry:
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -189,9 +191,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8(
<vscale x 8 x i8>,
<vscale x 16 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
@@ -202,7 +204,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 16 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -212,9 +214,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 8 x i8>,
<vscale x 16 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
@@ -226,7 +228,7 @@ entry:
<vscale x 16 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 16 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -235,9 +237,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8(
<vscale x 8 x i8>,
<vscale x 32 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
@@ -248,7 +250,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 32 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -258,9 +260,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 8 x i8>,
<vscale x 32 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
@@ -272,7 +274,7 @@ entry:
<vscale x 32 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 32 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -281,9 +283,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16(
<vscale x 4 x i16>,
<vscale x 1 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
@@ -294,7 +296,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 1 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -304,9 +306,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 4 x i16>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
@@ -318,7 +320,7 @@ entry:
<vscale x 1 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -327,9 +329,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv2i16(
<vscale x 4 x i16>,
<vscale x 2 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
@@ -340,7 +342,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 2 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -350,9 +352,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 4 x i16>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
@@ -364,7 +366,7 @@ entry:
<vscale x 2 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -373,9 +375,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
@@ -386,7 +388,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -396,9 +398,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
@@ -410,7 +412,7 @@ entry:
<vscale x 4 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -419,9 +421,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv8i16(
<vscale x 4 x i16>,
<vscale x 8 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
@@ -432,7 +434,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 8 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -442,9 +444,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 4 x i16>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
@@ -456,7 +458,7 @@ entry:
<vscale x 8 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -465,9 +467,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv16i16(
<vscale x 4 x i16>,
<vscale x 16 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
@@ -478,7 +480,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 16 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -488,9 +490,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 4 x i16>,
<vscale x 16 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
@@ -502,7 +504,7 @@ entry:
<vscale x 16 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 16 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -511,9 +513,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv32i16(
<vscale x 4 x i16>,
<vscale x 32 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
@@ -524,7 +526,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 32 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -534,9 +536,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 4 x i16>,
<vscale x 32 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
@@ -548,7 +550,7 @@ entry:
<vscale x 32 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 32 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -557,9 +559,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv1i32(
<vscale x 2 x i32>,
<vscale x 1 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
@@ -570,7 +572,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 1 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -580,9 +582,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 2 x i32>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
@@ -594,7 +596,7 @@ entry:
<vscale x 1 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -603,9 +605,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
@@ -616,7 +618,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -626,9 +628,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
@@ -640,7 +642,7 @@ entry:
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -649,9 +651,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv4i32(
<vscale x 2 x i32>,
<vscale x 4 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
@@ -662,7 +664,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 4 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -672,9 +674,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 2 x i32>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
@@ -686,7 +688,7 @@ entry:
<vscale x 4 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -695,9 +697,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv8i32(
<vscale x 2 x i32>,
<vscale x 8 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
@@ -708,7 +710,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 8 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -718,9 +720,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 2 x i32>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
@@ -732,7 +734,7 @@ entry:
<vscale x 8 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -741,9 +743,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv16i32(
<vscale x 2 x i32>,
<vscale x 16 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
@@ -754,7 +756,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 16 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -764,9 +766,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 2 x i32>,
<vscale x 16 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
@@ -778,7 +780,7 @@ entry:
<vscale x 16 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 16 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -787,9 +789,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i64>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredminu_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredminu_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
@@ -800,7 +802,7 @@ entry:
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
<vscale x 1 x i64> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 1 x i64> %a
}
@@ -810,9 +812,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredminu_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredminu_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
@@ -824,7 +826,7 @@ entry:
<vscale x 1 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i64> %a
}
@@ -833,9 +835,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv2i64(
<vscale x 1 x i64>,
<vscale x 2 x i64>,
<vscale x 1 x i64>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredminu_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredminu_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
@@ -846,7 +848,7 @@ entry:
<vscale x 1 x i64> %0,
<vscale x 2 x i64> %1,
<vscale x 1 x i64> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 1 x i64> %a
}
@@ -856,9 +858,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 1 x i64>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredminu_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredminu_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
@@ -870,7 +872,7 @@ entry:
<vscale x 2 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i64> %a
}
@@ -879,9 +881,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv4i64(
<vscale x 1 x i64>,
<vscale x 4 x i64>,
<vscale x 1 x i64>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredminu_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredminu_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
@@ -892,7 +894,7 @@ entry:
<vscale x 1 x i64> %0,
<vscale x 4 x i64> %1,
<vscale x 1 x i64> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 1 x i64> %a
}
@@ -902,9 +904,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 1 x i64>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredminu_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredminu_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
@@ -916,7 +918,7 @@ entry:
<vscale x 4 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i64> %a
}
@@ -925,9 +927,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv8i64(
<vscale x 1 x i64>,
<vscale x 8 x i64>,
<vscale x 1 x i64>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredminu_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredminu_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
@@ -938,7 +940,7 @@ entry:
<vscale x 1 x i64> %0,
<vscale x 8 x i64> %1,
<vscale x 1 x i64> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 1 x i64> %a
}
@@ -948,9 +950,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 1 x i64>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredminu_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredminu_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
@@ -962,7 +964,7 @@ entry:
<vscale x 8 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i64> %a
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll
deleted file mode 100644
index 27ecdcfa6ccf19..00000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll
+++ /dev/null
@@ -1,968 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
-declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8(
- <vscale x 8 x i8>,
- <vscale x 1 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv1i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vredor.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8(
- <vscale x 8 x i8> %0,
- <vscale x 1 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv1i8(
- <vscale x 8 x i8>,
- <vscale x 1 x i8>,
- <vscale x 8 x i8>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv1i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv1i8(
- <vscale x 8 x i8> %0,
- <vscale x 1 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8(
- <vscale x 8 x i8>,
- <vscale x 2 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv2i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vredor.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8(
- <vscale x 8 x i8> %0,
- <vscale x 2 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv2i8(
- <vscale x 8 x i8>,
- <vscale x 2 x i8>,
- <vscale x 8 x i8>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv2i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv2i8(
- <vscale x 8 x i8> %0,
- <vscale x 2 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8(
- <vscale x 8 x i8>,
- <vscale x 4 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv4i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vredor.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8(
- <vscale x 8 x i8> %0,
- <vscale x 4 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv4i8(
- <vscale x 8 x i8>,
- <vscale x 4 x i8>,
- <vscale x 8 x i8>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv4i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv4i8(
- <vscale x 8 x i8> %0,
- <vscale x 4 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv8i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vredor.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv8i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv8i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv8i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8(
- <vscale x 8 x i8>,
- <vscale x 16 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv16i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vredor.vs v8, v10, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8(
- <vscale x 8 x i8> %0,
- <vscale x 16 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv16i8(
- <vscale x 8 x i8>,
- <vscale x 16 x i8>,
- <vscale x 8 x i8>,
- <vscale x 16 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv16i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vredor.vs v8, v10, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv16i8(
- <vscale x 8 x i8> %0,
- <vscale x 16 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 16 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8(
- <vscale x 8 x i8>,
- <vscale x 32 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv32i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vredor.vs v8, v12, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8(
- <vscale x 8 x i8> %0,
- <vscale x 32 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv32i8(
- <vscale x 8 x i8>,
- <vscale x 32 x i8>,
- <vscale x 8 x i8>,
- <vscale x 32 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv32i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vredor.vs v8, v12, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv32i8(
- <vscale x 8 x i8> %0,
- <vscale x 32 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 32 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16(
- <vscale x 4 x i16>,
- <vscale x 1 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv1i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vredor.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16(
- <vscale x 4 x i16> %0,
- <vscale x 1 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv1i16(
- <vscale x 4 x i16>,
- <vscale x 1 x i16>,
- <vscale x 4 x i16>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv1i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv1i16(
- <vscale x 4 x i16> %0,
- <vscale x 1 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv2i16(
- <vscale x 4 x i16>,
- <vscale x 2 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv2i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vredor.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv2i16(
- <vscale x 4 x i16> %0,
- <vscale x 2 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv2i16(
- <vscale x 4 x i16>,
- <vscale x 2 x i16>,
- <vscale x 4 x i16>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv2i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv2i16(
- <vscale x 4 x i16> %0,
- <vscale x 2 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv4i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv4i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vredor.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv4i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv4i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv4i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv4i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv8i16(
- <vscale x 4 x i16>,
- <vscale x 8 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv8i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vredor.vs v8, v10, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv8i16(
- <vscale x 4 x i16> %0,
- <vscale x 8 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv8i16(
- <vscale x 4 x i16>,
- <vscale x 8 x i16>,
- <vscale x 4 x i16>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv8i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vredor.vs v8, v10, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv8i16(
- <vscale x 4 x i16> %0,
- <vscale x 8 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv16i16(
- <vscale x 4 x i16>,
- <vscale x 16 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv16i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vredor.vs v8, v12, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv16i16(
- <vscale x 4 x i16> %0,
- <vscale x 16 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv16i16(
- <vscale x 4 x i16>,
- <vscale x 16 x i16>,
- <vscale x 4 x i16>,
- <vscale x 16 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv16i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vredor.vs v8, v12, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv16i16(
- <vscale x 4 x i16> %0,
- <vscale x 16 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 16 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv32i16(
- <vscale x 4 x i16>,
- <vscale x 32 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv32i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vredor.vs v8, v16, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv32i16(
- <vscale x 4 x i16> %0,
- <vscale x 32 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv32i16(
- <vscale x 4 x i16>,
- <vscale x 32 x i16>,
- <vscale x 4 x i16>,
- <vscale x 32 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv32i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vredor.vs v8, v16, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv32i16(
- <vscale x 4 x i16> %0,
- <vscale x 32 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 32 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv1i32(
- <vscale x 2 x i32>,
- <vscale x 1 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv1i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vredor.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv1i32(
- <vscale x 2 x i32> %0,
- <vscale x 1 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv1i32(
- <vscale x 2 x i32>,
- <vscale x 1 x i32>,
- <vscale x 2 x i32>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv1i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv1i32(
- <vscale x 2 x i32> %0,
- <vscale x 1 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv2i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vredor.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv2i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv2i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv2i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv4i32(
- <vscale x 2 x i32>,
- <vscale x 4 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv4i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vredor.vs v8, v10, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv4i32(
- <vscale x 2 x i32> %0,
- <vscale x 4 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv4i32(
- <vscale x 2 x i32>,
- <vscale x 4 x i32>,
- <vscale x 2 x i32>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv4i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vredor.vs v8, v10, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv4i32(
- <vscale x 2 x i32> %0,
- <vscale x 4 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv8i32(
- <vscale x 2 x i32>,
- <vscale x 8 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv8i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vredor.vs v8, v12, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv8i32(
- <vscale x 2 x i32> %0,
- <vscale x 8 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv8i32(
- <vscale x 2 x i32>,
- <vscale x 8 x i32>,
- <vscale x 2 x i32>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv8i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vredor.vs v8, v12, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv8i32(
- <vscale x 2 x i32> %0,
- <vscale x 8 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv16i32(
- <vscale x 2 x i32>,
- <vscale x 16 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv16i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vredor.vs v8, v16, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv16i32(
- <vscale x 2 x i32> %0,
- <vscale x 16 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv16i32(
- <vscale x 2 x i32>,
- <vscale x 16 x i32>,
- <vscale x 2 x i32>,
- <vscale x 16 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv16i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vredor.vs v8, v16, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv16i32(
- <vscale x 2 x i32> %0,
- <vscale x 16 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 16 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv1i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredor_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredor_vs_nxv1i64_nxv1i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vredor.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv1i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- <vscale x 1 x i64> %2,
- i64 %3)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv1i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredor_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv1i64_nxv1i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv1i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv2i64(
- <vscale x 1 x i64>,
- <vscale x 2 x i64>,
- <vscale x 1 x i64>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredor_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredor_vs_nxv1i64_nxv2i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vredor.vs v8, v10, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv2i64(
- <vscale x 1 x i64> %0,
- <vscale x 2 x i64> %1,
- <vscale x 1 x i64> %2,
- i64 %3)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv2i64(
- <vscale x 1 x i64>,
- <vscale x 2 x i64>,
- <vscale x 1 x i64>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredor_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv1i64_nxv2i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vredor.vs v8, v10, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv2i64(
- <vscale x 1 x i64> %0,
- <vscale x 2 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv4i64(
- <vscale x 1 x i64>,
- <vscale x 4 x i64>,
- <vscale x 1 x i64>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredor_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredor_vs_nxv1i64_nxv4i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vredor.vs v8, v12, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv4i64(
- <vscale x 1 x i64> %0,
- <vscale x 4 x i64> %1,
- <vscale x 1 x i64> %2,
- i64 %3)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv4i64(
- <vscale x 1 x i64>,
- <vscale x 4 x i64>,
- <vscale x 1 x i64>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredor_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv1i64_nxv4i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vredor.vs v8, v12, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv4i64(
- <vscale x 1 x i64> %0,
- <vscale x 4 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv8i64(
- <vscale x 1 x i64>,
- <vscale x 8 x i64>,
- <vscale x 1 x i64>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredor_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredor_vs_nxv1i64_nxv8i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vredor.vs v8, v16, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv8i64(
- <vscale x 1 x i64> %0,
- <vscale x 8 x i64> %1,
- <vscale x 1 x i64> %2,
- i64 %3)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv8i64(
- <vscale x 1 x i64>,
- <vscale x 8 x i64>,
- <vscale x 1 x i64>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredor_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv1i64_nxv8i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vredor.vs v8, v16, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv8i64(
- <vscale x 1 x i64> %0,
- <vscale x 8 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i64> %a
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vredor.ll
similarity index 90%
rename from llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll
rename to llvm/test/CodeGen/RISCV/rvv/vredor.ll
index 52728b8b39c25c..42096c6a5e9391 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vredor.ll
@@ -1,13 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s
declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8(
<vscale x 8 x i8>,
<vscale x 1 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
@@ -18,7 +20,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 1 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -28,9 +30,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 8 x i8>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
@@ -42,7 +44,7 @@ entry:
<vscale x 1 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -51,9 +53,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8(
<vscale x 8 x i8>,
<vscale x 2 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
@@ -64,7 +66,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 2 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -74,9 +76,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 8 x i8>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
@@ -88,7 +90,7 @@ entry:
<vscale x 2 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -97,9 +99,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8(
<vscale x 8 x i8>,
<vscale x 4 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
@@ -110,7 +112,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 4 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -120,9 +122,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 8 x i8>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
@@ -134,7 +136,7 @@ entry:
<vscale x 4 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -143,9 +145,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
@@ -156,7 +158,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -166,9 +168,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
@@ -180,7 +182,7 @@ entry:
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -189,9 +191,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8(
<vscale x 8 x i8>,
<vscale x 16 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
@@ -202,7 +204,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 16 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -212,9 +214,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 8 x i8>,
<vscale x 16 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
@@ -226,7 +228,7 @@ entry:
<vscale x 16 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 16 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -235,9 +237,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8(
<vscale x 8 x i8>,
<vscale x 32 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
@@ -248,7 +250,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 32 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -258,9 +260,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 8 x i8>,
<vscale x 32 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
@@ -272,7 +274,7 @@ entry:
<vscale x 32 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 32 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -281,9 +283,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16(
<vscale x 4 x i16>,
<vscale x 1 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
@@ -294,7 +296,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 1 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -304,9 +306,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 4 x i16>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
@@ -318,7 +320,7 @@ entry:
<vscale x 1 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -327,9 +329,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv2i16(
<vscale x 4 x i16>,
<vscale x 2 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
@@ -340,7 +342,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 2 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -350,9 +352,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 4 x i16>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
@@ -364,7 +366,7 @@ entry:
<vscale x 2 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -373,9 +375,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
@@ -386,7 +388,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -396,9 +398,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
@@ -410,7 +412,7 @@ entry:
<vscale x 4 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -419,9 +421,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv8i16(
<vscale x 4 x i16>,
<vscale x 8 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
@@ -432,7 +434,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 8 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -442,9 +444,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 4 x i16>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
@@ -456,7 +458,7 @@ entry:
<vscale x 8 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -465,9 +467,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv16i16(
<vscale x 4 x i16>,
<vscale x 16 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
@@ -478,7 +480,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 16 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -488,9 +490,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 4 x i16>,
<vscale x 16 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
@@ -502,7 +504,7 @@ entry:
<vscale x 16 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 16 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -511,9 +513,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv32i16(
<vscale x 4 x i16>,
<vscale x 32 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
@@ -524,7 +526,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 32 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -534,9 +536,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 4 x i16>,
<vscale x 32 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
@@ -548,7 +550,7 @@ entry:
<vscale x 32 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 32 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -557,9 +559,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv1i32(
<vscale x 2 x i32>,
<vscale x 1 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
@@ -570,7 +572,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 1 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -580,9 +582,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 2 x i32>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
@@ -594,7 +596,7 @@ entry:
<vscale x 1 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -603,9 +605,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
@@ -616,7 +618,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -626,9 +628,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
@@ -640,7 +642,7 @@ entry:
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -649,9 +651,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv4i32(
<vscale x 2 x i32>,
<vscale x 4 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
@@ -662,7 +664,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 4 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -672,9 +674,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 2 x i32>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
@@ -686,7 +688,7 @@ entry:
<vscale x 4 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -695,9 +697,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv8i32(
<vscale x 2 x i32>,
<vscale x 8 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
@@ -708,7 +710,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 8 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -718,9 +720,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 2 x i32>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
@@ -732,7 +734,7 @@ entry:
<vscale x 8 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -741,9 +743,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv16i32(
<vscale x 2 x i32>,
<vscale x 16 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
@@ -754,7 +756,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 16 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -764,9 +766,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 2 x i32>,
<vscale x 16 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
@@ -778,7 +780,7 @@ entry:
<vscale x 16 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 16 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -787,9 +789,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i64>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredor_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredor_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
@@ -800,7 +802,7 @@ entry:
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
<vscale x 1 x i64> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 1 x i64> %a
}
@@ -810,9 +812,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredor_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredor_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
@@ -824,7 +826,7 @@ entry:
<vscale x 1 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i64> %a
}
@@ -833,9 +835,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv2i64(
<vscale x 1 x i64>,
<vscale x 2 x i64>,
<vscale x 1 x i64>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredor_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredor_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
@@ -846,7 +848,7 @@ entry:
<vscale x 1 x i64> %0,
<vscale x 2 x i64> %1,
<vscale x 1 x i64> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 1 x i64> %a
}
@@ -856,9 +858,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 1 x i64>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredor_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredor_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
@@ -870,7 +872,7 @@ entry:
<vscale x 2 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i64> %a
}
@@ -879,9 +881,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv4i64(
<vscale x 1 x i64>,
<vscale x 4 x i64>,
<vscale x 1 x i64>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredor_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredor_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
@@ -892,7 +894,7 @@ entry:
<vscale x 1 x i64> %0,
<vscale x 4 x i64> %1,
<vscale x 1 x i64> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 1 x i64> %a
}
@@ -902,9 +904,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 1 x i64>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredor_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredor_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
@@ -916,7 +918,7 @@ entry:
<vscale x 4 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i64> %a
}
@@ -925,9 +927,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv8i64(
<vscale x 1 x i64>,
<vscale x 8 x i64>,
<vscale x 1 x i64>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredor_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredor_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
@@ -938,7 +940,7 @@ entry:
<vscale x 1 x i64> %0,
<vscale x 8 x i64> %1,
<vscale x 1 x i64> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 1 x i64> %a
}
@@ -948,9 +950,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 1 x i64>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredor_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredor_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
@@ -962,7 +964,7 @@ entry:
<vscale x 8 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i64> %a
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll
deleted file mode 100644
index f77ecafdf773d2..00000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll
+++ /dev/null
@@ -1,968 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
-declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8(
- <vscale x 8 x i8>,
- <vscale x 1 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv1i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8(
- <vscale x 8 x i8> %0,
- <vscale x 1 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv1i8(
- <vscale x 8 x i8>,
- <vscale x 1 x i8>,
- <vscale x 8 x i8>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv1i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv1i8(
- <vscale x 8 x i8> %0,
- <vscale x 1 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8(
- <vscale x 8 x i8>,
- <vscale x 2 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv2i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8(
- <vscale x 8 x i8> %0,
- <vscale x 2 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv2i8(
- <vscale x 8 x i8>,
- <vscale x 2 x i8>,
- <vscale x 8 x i8>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv2i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv2i8(
- <vscale x 8 x i8> %0,
- <vscale x 2 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8(
- <vscale x 8 x i8>,
- <vscale x 4 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv4i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8(
- <vscale x 8 x i8> %0,
- <vscale x 4 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv4i8(
- <vscale x 8 x i8>,
- <vscale x 4 x i8>,
- <vscale x 8 x i8>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv4i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv4i8(
- <vscale x 8 x i8> %0,
- <vscale x 4 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv8i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv8i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv8i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv8i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8(
- <vscale x 8 x i8>,
- <vscale x 16 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv16i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v10, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8(
- <vscale x 8 x i8> %0,
- <vscale x 16 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv16i8(
- <vscale x 8 x i8>,
- <vscale x 16 x i8>,
- <vscale x 8 x i8>,
- <vscale x 16 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv16i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v10, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv16i8(
- <vscale x 8 x i8> %0,
- <vscale x 16 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 16 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8(
- <vscale x 8 x i8>,
- <vscale x 32 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv32i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v12, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8(
- <vscale x 8 x i8> %0,
- <vscale x 32 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv32i8(
- <vscale x 8 x i8>,
- <vscale x 32 x i8>,
- <vscale x 8 x i8>,
- <vscale x 32 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv32i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v12, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv32i8(
- <vscale x 8 x i8> %0,
- <vscale x 32 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 32 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16(
- <vscale x 4 x i16>,
- <vscale x 1 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv1i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16(
- <vscale x 4 x i16> %0,
- <vscale x 1 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv1i16(
- <vscale x 4 x i16>,
- <vscale x 1 x i16>,
- <vscale x 4 x i16>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv1i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv1i16(
- <vscale x 4 x i16> %0,
- <vscale x 1 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv2i16(
- <vscale x 4 x i16>,
- <vscale x 2 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv2i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv2i16(
- <vscale x 4 x i16> %0,
- <vscale x 2 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv2i16(
- <vscale x 4 x i16>,
- <vscale x 2 x i16>,
- <vscale x 4 x i16>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv2i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv2i16(
- <vscale x 4 x i16> %0,
- <vscale x 2 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv4i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv4i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv4i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv4i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv4i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv4i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv8i16(
- <vscale x 4 x i16>,
- <vscale x 8 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv8i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v10, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv8i16(
- <vscale x 4 x i16> %0,
- <vscale x 8 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv8i16(
- <vscale x 4 x i16>,
- <vscale x 8 x i16>,
- <vscale x 4 x i16>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv8i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v10, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv8i16(
- <vscale x 4 x i16> %0,
- <vscale x 8 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv16i16(
- <vscale x 4 x i16>,
- <vscale x 16 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv16i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v12, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv16i16(
- <vscale x 4 x i16> %0,
- <vscale x 16 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv16i16(
- <vscale x 4 x i16>,
- <vscale x 16 x i16>,
- <vscale x 4 x i16>,
- <vscale x 16 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv16i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v12, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv16i16(
- <vscale x 4 x i16> %0,
- <vscale x 16 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 16 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv32i16(
- <vscale x 4 x i16>,
- <vscale x 32 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv32i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v16, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv32i16(
- <vscale x 4 x i16> %0,
- <vscale x 32 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv32i16(
- <vscale x 4 x i16>,
- <vscale x 32 x i16>,
- <vscale x 4 x i16>,
- <vscale x 32 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv32i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v16, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv32i16(
- <vscale x 4 x i16> %0,
- <vscale x 32 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 32 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv1i32(
- <vscale x 2 x i32>,
- <vscale x 1 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv1i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv1i32(
- <vscale x 2 x i32> %0,
- <vscale x 1 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv1i32(
- <vscale x 2 x i32>,
- <vscale x 1 x i32>,
- <vscale x 2 x i32>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv1i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv1i32(
- <vscale x 2 x i32> %0,
- <vscale x 1 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv2i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv2i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv2i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv2i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv4i32(
- <vscale x 2 x i32>,
- <vscale x 4 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv4i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v10, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv4i32(
- <vscale x 2 x i32> %0,
- <vscale x 4 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv4i32(
- <vscale x 2 x i32>,
- <vscale x 4 x i32>,
- <vscale x 2 x i32>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv4i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v10, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv4i32(
- <vscale x 2 x i32> %0,
- <vscale x 4 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv8i32(
- <vscale x 2 x i32>,
- <vscale x 8 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv8i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v12, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv8i32(
- <vscale x 2 x i32> %0,
- <vscale x 8 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv8i32(
- <vscale x 2 x i32>,
- <vscale x 8 x i32>,
- <vscale x 2 x i32>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv8i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v12, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv8i32(
- <vscale x 2 x i32> %0,
- <vscale x 8 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv16i32(
- <vscale x 2 x i32>,
- <vscale x 16 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv16i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v16, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv16i32(
- <vscale x 2 x i32> %0,
- <vscale x 16 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv16i32(
- <vscale x 2 x i32>,
- <vscale x 16 x i32>,
- <vscale x 2 x i32>,
- <vscale x 16 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv16i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v16, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv16i32(
- <vscale x 2 x i32> %0,
- <vscale x 16 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 16 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv1i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredsum_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_vs_nxv1i64_nxv1i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv1i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- <vscale x 1 x i64> %2,
- i64 %3)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv1i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredsum_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv1i64_nxv1i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv1i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv2i64(
- <vscale x 1 x i64>,
- <vscale x 2 x i64>,
- <vscale x 1 x i64>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredsum_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_vs_nxv1i64_nxv2i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v10, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv2i64(
- <vscale x 1 x i64> %0,
- <vscale x 2 x i64> %1,
- <vscale x 1 x i64> %2,
- i64 %3)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv2i64(
- <vscale x 1 x i64>,
- <vscale x 2 x i64>,
- <vscale x 1 x i64>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredsum_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv1i64_nxv2i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v10, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv2i64(
- <vscale x 1 x i64> %0,
- <vscale x 2 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv4i64(
- <vscale x 1 x i64>,
- <vscale x 4 x i64>,
- <vscale x 1 x i64>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredsum_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_vs_nxv1i64_nxv4i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v12, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv4i64(
- <vscale x 1 x i64> %0,
- <vscale x 4 x i64> %1,
- <vscale x 1 x i64> %2,
- i64 %3)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv4i64(
- <vscale x 1 x i64>,
- <vscale x 4 x i64>,
- <vscale x 1 x i64>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredsum_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv1i64_nxv4i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v12, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv4i64(
- <vscale x 1 x i64> %0,
- <vscale x 4 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv8i64(
- <vscale x 1 x i64>,
- <vscale x 8 x i64>,
- <vscale x 1 x i64>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredsum_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_vs_nxv1i64_nxv8i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v16, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv8i64(
- <vscale x 1 x i64> %0,
- <vscale x 8 x i64> %1,
- <vscale x 1 x i64> %2,
- i64 %3)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv8i64(
- <vscale x 1 x i64>,
- <vscale x 8 x i64>,
- <vscale x 1 x i64>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredsum_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv1i64_nxv8i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vredsum.vs v8, v16, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv8i64(
- <vscale x 1 x i64> %0,
- <vscale x 8 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i64> %a
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vredsum.ll
similarity index 90%
rename from llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll
rename to llvm/test/CodeGen/RISCV/rvv/vredsum.ll
index 4d408b9f59e8e1..dec11c56771980 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vredsum.ll
@@ -1,13 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s
declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8(
<vscale x 8 x i8>,
<vscale x 1 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
@@ -18,7 +20,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 1 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -28,9 +30,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 8 x i8>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
@@ -42,7 +44,7 @@ entry:
<vscale x 1 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -51,9 +53,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8(
<vscale x 8 x i8>,
<vscale x 2 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
@@ -64,7 +66,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 2 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -74,9 +76,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 8 x i8>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
@@ -88,7 +90,7 @@ entry:
<vscale x 2 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -97,9 +99,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8(
<vscale x 8 x i8>,
<vscale x 4 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
@@ -110,7 +112,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 4 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -120,9 +122,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 8 x i8>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
@@ -134,7 +136,7 @@ entry:
<vscale x 4 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -143,9 +145,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
@@ -156,7 +158,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -166,9 +168,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
@@ -180,7 +182,7 @@ entry:
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -189,9 +191,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8(
<vscale x 8 x i8>,
<vscale x 16 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
@@ -202,7 +204,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 16 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -212,9 +214,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 8 x i8>,
<vscale x 16 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
@@ -226,7 +228,7 @@ entry:
<vscale x 16 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 16 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -235,9 +237,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8(
<vscale x 8 x i8>,
<vscale x 32 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
@@ -248,7 +250,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 32 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -258,9 +260,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 8 x i8>,
<vscale x 32 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
@@ -272,7 +274,7 @@ entry:
<vscale x 32 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 32 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -281,9 +283,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16(
<vscale x 4 x i16>,
<vscale x 1 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
@@ -294,7 +296,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 1 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -304,9 +306,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 4 x i16>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
@@ -318,7 +320,7 @@ entry:
<vscale x 1 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -327,9 +329,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv2i16(
<vscale x 4 x i16>,
<vscale x 2 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
@@ -340,7 +342,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 2 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -350,9 +352,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 4 x i16>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
@@ -364,7 +366,7 @@ entry:
<vscale x 2 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -373,9 +375,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
@@ -386,7 +388,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -396,9 +398,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
@@ -410,7 +412,7 @@ entry:
<vscale x 4 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -419,9 +421,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv8i16(
<vscale x 4 x i16>,
<vscale x 8 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
@@ -432,7 +434,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 8 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -442,9 +444,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 4 x i16>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
@@ -456,7 +458,7 @@ entry:
<vscale x 8 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -465,9 +467,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv16i16(
<vscale x 4 x i16>,
<vscale x 16 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
@@ -478,7 +480,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 16 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -488,9 +490,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 4 x i16>,
<vscale x 16 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
@@ -502,7 +504,7 @@ entry:
<vscale x 16 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 16 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -511,9 +513,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv32i16(
<vscale x 4 x i16>,
<vscale x 32 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
@@ -524,7 +526,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 32 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -534,9 +536,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 4 x i16>,
<vscale x 32 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
@@ -548,7 +550,7 @@ entry:
<vscale x 32 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 32 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -557,9 +559,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv1i32(
<vscale x 2 x i32>,
<vscale x 1 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
@@ -570,7 +572,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 1 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -580,9 +582,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 2 x i32>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
@@ -594,7 +596,7 @@ entry:
<vscale x 1 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -603,9 +605,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
@@ -616,7 +618,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -626,9 +628,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
@@ -640,7 +642,7 @@ entry:
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -649,9 +651,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv4i32(
<vscale x 2 x i32>,
<vscale x 4 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
@@ -662,7 +664,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 4 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -672,9 +674,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 2 x i32>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
@@ -686,7 +688,7 @@ entry:
<vscale x 4 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -695,9 +697,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv8i32(
<vscale x 2 x i32>,
<vscale x 8 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
@@ -708,7 +710,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 8 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -718,9 +720,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 2 x i32>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
@@ -732,7 +734,7 @@ entry:
<vscale x 8 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -741,9 +743,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv16i32(
<vscale x 2 x i32>,
<vscale x 16 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
@@ -754,7 +756,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 16 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -764,9 +766,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 2 x i32>,
<vscale x 16 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
@@ -778,7 +780,7 @@ entry:
<vscale x 16 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 16 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -787,9 +789,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i64>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredsum_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredsum_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
@@ -800,7 +802,7 @@ entry:
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
<vscale x 1 x i64> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 1 x i64> %a
}
@@ -810,9 +812,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredsum_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredsum_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
@@ -824,7 +826,7 @@ entry:
<vscale x 1 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i64> %a
}
@@ -833,9 +835,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv2i64(
<vscale x 1 x i64>,
<vscale x 2 x i64>,
<vscale x 1 x i64>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredsum_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredsum_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
@@ -846,7 +848,7 @@ entry:
<vscale x 1 x i64> %0,
<vscale x 2 x i64> %1,
<vscale x 1 x i64> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 1 x i64> %a
}
@@ -856,9 +858,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 1 x i64>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredsum_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredsum_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
@@ -870,7 +872,7 @@ entry:
<vscale x 2 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i64> %a
}
@@ -879,9 +881,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv4i64(
<vscale x 1 x i64>,
<vscale x 4 x i64>,
<vscale x 1 x i64>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredsum_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredsum_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
@@ -892,7 +894,7 @@ entry:
<vscale x 1 x i64> %0,
<vscale x 4 x i64> %1,
<vscale x 1 x i64> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 1 x i64> %a
}
@@ -902,9 +904,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 1 x i64>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredsum_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredsum_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
@@ -916,7 +918,7 @@ entry:
<vscale x 4 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i64> %a
}
@@ -925,9 +927,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv8i64(
<vscale x 1 x i64>,
<vscale x 8 x i64>,
<vscale x 1 x i64>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredsum_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredsum_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
@@ -938,7 +940,7 @@ entry:
<vscale x 1 x i64> %0,
<vscale x 8 x i64> %1,
<vscale x 1 x i64> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 1 x i64> %a
}
@@ -948,9 +950,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 1 x i64>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredsum_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredsum_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
@@ -962,7 +964,7 @@ entry:
<vscale x 8 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i64> %a
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll
deleted file mode 100644
index e74e56215990bb..00000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll
+++ /dev/null
@@ -1,968 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
-declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8(
- <vscale x 8 x i8>,
- <vscale x 1 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv1i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8(
- <vscale x 8 x i8> %0,
- <vscale x 1 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv1i8(
- <vscale x 8 x i8>,
- <vscale x 1 x i8>,
- <vscale x 8 x i8>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv1i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv1i8(
- <vscale x 8 x i8> %0,
- <vscale x 1 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8(
- <vscale x 8 x i8>,
- <vscale x 2 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv2i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8(
- <vscale x 8 x i8> %0,
- <vscale x 2 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv2i8(
- <vscale x 8 x i8>,
- <vscale x 2 x i8>,
- <vscale x 8 x i8>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv2i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv2i8(
- <vscale x 8 x i8> %0,
- <vscale x 2 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8(
- <vscale x 8 x i8>,
- <vscale x 4 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv4i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8(
- <vscale x 8 x i8> %0,
- <vscale x 4 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv4i8(
- <vscale x 8 x i8>,
- <vscale x 4 x i8>,
- <vscale x 8 x i8>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv4i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv4i8(
- <vscale x 8 x i8> %0,
- <vscale x 4 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv8i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv8i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv8i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv8i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8(
- <vscale x 8 x i8>,
- <vscale x 16 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv16i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v10, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8(
- <vscale x 8 x i8> %0,
- <vscale x 16 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv16i8(
- <vscale x 8 x i8>,
- <vscale x 16 x i8>,
- <vscale x 8 x i8>,
- <vscale x 16 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv16i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v10, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv16i8(
- <vscale x 8 x i8> %0,
- <vscale x 16 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 16 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8(
- <vscale x 8 x i8>,
- <vscale x 32 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv32i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v12, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8(
- <vscale x 8 x i8> %0,
- <vscale x 32 x i8> %1,
- <vscale x 8 x i8> %2,
- i64 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv32i8(
- <vscale x 8 x i8>,
- <vscale x 32 x i8>,
- <vscale x 8 x i8>,
- <vscale x 32 x i1>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv32i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v12, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv32i8(
- <vscale x 8 x i8> %0,
- <vscale x 32 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 32 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16(
- <vscale x 4 x i16>,
- <vscale x 1 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv1i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16(
- <vscale x 4 x i16> %0,
- <vscale x 1 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv1i16(
- <vscale x 4 x i16>,
- <vscale x 1 x i16>,
- <vscale x 4 x i16>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv1i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv1i16(
- <vscale x 4 x i16> %0,
- <vscale x 1 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv2i16(
- <vscale x 4 x i16>,
- <vscale x 2 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv2i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv2i16(
- <vscale x 4 x i16> %0,
- <vscale x 2 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv2i16(
- <vscale x 4 x i16>,
- <vscale x 2 x i16>,
- <vscale x 4 x i16>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv2i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv2i16(
- <vscale x 4 x i16> %0,
- <vscale x 2 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv4i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv4i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv4i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv4i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv4i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv4i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv8i16(
- <vscale x 4 x i16>,
- <vscale x 8 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv8i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v10, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv8i16(
- <vscale x 4 x i16> %0,
- <vscale x 8 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv8i16(
- <vscale x 4 x i16>,
- <vscale x 8 x i16>,
- <vscale x 4 x i16>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv8i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v10, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv8i16(
- <vscale x 4 x i16> %0,
- <vscale x 8 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv16i16(
- <vscale x 4 x i16>,
- <vscale x 16 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv16i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v12, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv16i16(
- <vscale x 4 x i16> %0,
- <vscale x 16 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv16i16(
- <vscale x 4 x i16>,
- <vscale x 16 x i16>,
- <vscale x 4 x i16>,
- <vscale x 16 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv16i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v12, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv16i16(
- <vscale x 4 x i16> %0,
- <vscale x 16 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 16 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv32i16(
- <vscale x 4 x i16>,
- <vscale x 32 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv32i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v16, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv32i16(
- <vscale x 4 x i16> %0,
- <vscale x 32 x i16> %1,
- <vscale x 4 x i16> %2,
- i64 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv32i16(
- <vscale x 4 x i16>,
- <vscale x 32 x i16>,
- <vscale x 4 x i16>,
- <vscale x 32 x i1>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv32i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v16, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv32i16(
- <vscale x 4 x i16> %0,
- <vscale x 32 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 32 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv1i32(
- <vscale x 2 x i32>,
- <vscale x 1 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv1i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv1i32(
- <vscale x 2 x i32> %0,
- <vscale x 1 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv1i32(
- <vscale x 2 x i32>,
- <vscale x 1 x i32>,
- <vscale x 2 x i32>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv1i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv1i32(
- <vscale x 2 x i32> %0,
- <vscale x 1 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv2i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv2i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv2i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv2i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv4i32(
- <vscale x 2 x i32>,
- <vscale x 4 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv4i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v10, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv4i32(
- <vscale x 2 x i32> %0,
- <vscale x 4 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv4i32(
- <vscale x 2 x i32>,
- <vscale x 4 x i32>,
- <vscale x 2 x i32>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv4i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v10, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv4i32(
- <vscale x 2 x i32> %0,
- <vscale x 4 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv8i32(
- <vscale x 2 x i32>,
- <vscale x 8 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv8i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v12, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv8i32(
- <vscale x 2 x i32> %0,
- <vscale x 8 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv8i32(
- <vscale x 2 x i32>,
- <vscale x 8 x i32>,
- <vscale x 2 x i32>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv8i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v12, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv8i32(
- <vscale x 2 x i32> %0,
- <vscale x 8 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv16i32(
- <vscale x 2 x i32>,
- <vscale x 16 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv16i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v16, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv16i32(
- <vscale x 2 x i32> %0,
- <vscale x 16 x i32> %1,
- <vscale x 2 x i32> %2,
- i64 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv16i32(
- <vscale x 2 x i32>,
- <vscale x 16 x i32>,
- <vscale x 2 x i32>,
- <vscale x 16 x i1>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv16i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v16, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv16i32(
- <vscale x 2 x i32> %0,
- <vscale x 16 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 16 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv1i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredxor_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_vs_nxv1i64_nxv1i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v9, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv1i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- <vscale x 1 x i64> %2,
- i64 %3)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv1i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredxor_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv1i64_nxv1i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv1i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv2i64(
- <vscale x 1 x i64>,
- <vscale x 2 x i64>,
- <vscale x 1 x i64>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredxor_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_vs_nxv1i64_nxv2i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v10, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv2i64(
- <vscale x 1 x i64> %0,
- <vscale x 2 x i64> %1,
- <vscale x 1 x i64> %2,
- i64 %3)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv2i64(
- <vscale x 1 x i64>,
- <vscale x 2 x i64>,
- <vscale x 1 x i64>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredxor_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv1i64_nxv2i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v10, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv2i64(
- <vscale x 1 x i64> %0,
- <vscale x 2 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv4i64(
- <vscale x 1 x i64>,
- <vscale x 4 x i64>,
- <vscale x 1 x i64>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredxor_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_vs_nxv1i64_nxv4i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v12, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv4i64(
- <vscale x 1 x i64> %0,
- <vscale x 4 x i64> %1,
- <vscale x 1 x i64> %2,
- i64 %3)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv4i64(
- <vscale x 1 x i64>,
- <vscale x 4 x i64>,
- <vscale x 1 x i64>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredxor_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv1i64_nxv4i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v12, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv4i64(
- <vscale x 1 x i64> %0,
- <vscale x 4 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv8i64(
- <vscale x 1 x i64>,
- <vscale x 8 x i64>,
- <vscale x 1 x i64>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredxor_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_vs_nxv1i64_nxv8i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v16, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv8i64(
- <vscale x 1 x i64> %0,
- <vscale x 8 x i64> %1,
- <vscale x 1 x i64> %2,
- i64 %3)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv8i64(
- <vscale x 1 x i64>,
- <vscale x 8 x i64>,
- <vscale x 1 x i64>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vredxor_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv1i64_nxv8i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v16, v9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv8i64(
- <vscale x 1 x i64> %0,
- <vscale x 8 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i64> %a
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vredxor.ll
similarity index 90%
rename from llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll
rename to llvm/test/CodeGen/RISCV/rvv/vredxor.ll
index a66b27c8398f0a..acdf396b56c11d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vredxor.ll
@@ -1,13 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s
declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8(
<vscale x 8 x i8>,
<vscale x 1 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
@@ -18,7 +20,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 1 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -28,9 +30,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 8 x i8>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
@@ -42,7 +44,7 @@ entry:
<vscale x 1 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -51,9 +53,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8(
<vscale x 8 x i8>,
<vscale x 2 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
@@ -64,7 +66,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 2 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -74,9 +76,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 8 x i8>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
@@ -88,7 +90,7 @@ entry:
<vscale x 2 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -97,9 +99,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8(
<vscale x 8 x i8>,
<vscale x 4 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
@@ -110,7 +112,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 4 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -120,9 +122,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 8 x i8>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
@@ -134,7 +136,7 @@ entry:
<vscale x 4 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -143,9 +145,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
@@ -156,7 +158,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -166,9 +168,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
@@ -180,7 +182,7 @@ entry:
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -189,9 +191,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8(
<vscale x 8 x i8>,
<vscale x 16 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
@@ -202,7 +204,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 16 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -212,9 +214,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 8 x i8>,
<vscale x 16 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
@@ -226,7 +228,7 @@ entry:
<vscale x 16 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 16 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -235,9 +237,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8(
<vscale x 8 x i8>,
<vscale x 32 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
@@ -248,7 +250,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 32 x i8> %1,
<vscale x 8 x i8> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -258,9 +260,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 8 x i8>,
<vscale x 32 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
@@ -272,7 +274,7 @@ entry:
<vscale x 32 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 32 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i8> %a
}
@@ -281,9 +283,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16(
<vscale x 4 x i16>,
<vscale x 1 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
@@ -294,7 +296,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 1 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -304,9 +306,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 4 x i16>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
@@ -318,7 +320,7 @@ entry:
<vscale x 1 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -327,9 +329,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv2i16(
<vscale x 4 x i16>,
<vscale x 2 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
@@ -340,7 +342,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 2 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -350,9 +352,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 4 x i16>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
@@ -364,7 +366,7 @@ entry:
<vscale x 2 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -373,9 +375,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
@@ -386,7 +388,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -396,9 +398,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
@@ -410,7 +412,7 @@ entry:
<vscale x 4 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -419,9 +421,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv8i16(
<vscale x 4 x i16>,
<vscale x 8 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
@@ -432,7 +434,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 8 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -442,9 +444,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 4 x i16>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
@@ -456,7 +458,7 @@ entry:
<vscale x 8 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -465,9 +467,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv16i16(
<vscale x 4 x i16>,
<vscale x 16 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
@@ -478,7 +480,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 16 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -488,9 +490,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 4 x i16>,
<vscale x 16 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
@@ -502,7 +504,7 @@ entry:
<vscale x 16 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 16 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -511,9 +513,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv32i16(
<vscale x 4 x i16>,
<vscale x 32 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
@@ -524,7 +526,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 32 x i16> %1,
<vscale x 4 x i16> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -534,9 +536,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 4 x i16>,
<vscale x 32 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
@@ -548,7 +550,7 @@ entry:
<vscale x 32 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 32 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i16> %a
}
@@ -557,9 +559,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv1i32(
<vscale x 2 x i32>,
<vscale x 1 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
@@ -570,7 +572,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 1 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -580,9 +582,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 2 x i32>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
@@ -594,7 +596,7 @@ entry:
<vscale x 1 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -603,9 +605,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
@@ -616,7 +618,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -626,9 +628,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
@@ -640,7 +642,7 @@ entry:
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -649,9 +651,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv4i32(
<vscale x 2 x i32>,
<vscale x 4 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
@@ -662,7 +664,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 4 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -672,9 +674,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 2 x i32>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
@@ -686,7 +688,7 @@ entry:
<vscale x 4 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -695,9 +697,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv8i32(
<vscale x 2 x i32>,
<vscale x 8 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
@@ -708,7 +710,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 8 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -718,9 +720,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 2 x i32>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
@@ -732,7 +734,7 @@ entry:
<vscale x 8 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -741,9 +743,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv16i32(
<vscale x 2 x i32>,
<vscale x 16 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
@@ -754,7 +756,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 16 x i32> %1,
<vscale x 2 x i32> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -764,9 +766,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 2 x i32>,
<vscale x 16 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
@@ -778,7 +780,7 @@ entry:
<vscale x 16 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 16 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i32> %a
}
@@ -787,9 +789,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i64>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredxor_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredxor_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
@@ -800,7 +802,7 @@ entry:
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
<vscale x 1 x i64> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 1 x i64> %a
}
@@ -810,9 +812,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredxor_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredxor_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
@@ -824,7 +826,7 @@ entry:
<vscale x 1 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i64> %a
}
@@ -833,9 +835,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv2i64(
<vscale x 1 x i64>,
<vscale x 2 x i64>,
<vscale x 1 x i64>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredxor_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredxor_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
@@ -846,7 +848,7 @@ entry:
<vscale x 1 x i64> %0,
<vscale x 2 x i64> %1,
<vscale x 1 x i64> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 1 x i64> %a
}
@@ -856,9 +858,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 1 x i64>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredxor_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredxor_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
@@ -870,7 +872,7 @@ entry:
<vscale x 2 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i64> %a
}
@@ -879,9 +881,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv4i64(
<vscale x 1 x i64>,
<vscale x 4 x i64>,
<vscale x 1 x i64>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredxor_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredxor_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
@@ -892,7 +894,7 @@ entry:
<vscale x 1 x i64> %0,
<vscale x 4 x i64> %1,
<vscale x 1 x i64> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 1 x i64> %a
}
@@ -902,9 +904,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 1 x i64>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredxor_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredxor_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
@@ -916,7 +918,7 @@ entry:
<vscale x 4 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i64> %a
}
@@ -925,9 +927,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv8i64(
<vscale x 1 x i64>,
<vscale x 8 x i64>,
<vscale x 1 x i64>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredxor_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredxor_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
@@ -938,7 +940,7 @@ entry:
<vscale x 1 x i64> %0,
<vscale x 8 x i64> %1,
<vscale x 1 x i64> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 1 x i64> %a
}
@@ -948,9 +950,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 1 x i64>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vredxor_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vredxor_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
@@ -962,7 +964,7 @@ entry:
<vscale x 8 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i64> %a
}
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