[PATCH] D154945: [TableGen] Enable multiple instructions in patterns

Tomas Matheson via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Jul 11 03:47:06 PDT 2023


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Tablegen patterns for instrucion selection can generate multiple
instructions, but only if there is a data dependency between them so
that they can be expressed as a DAG. For example, something like:

  (store (load %src), %dst)

For some patterns, we might want to generate a sequence of instructions
which do not have a data dependency. For example on AArch64 some atomic
instructions are implemented like this:

  LDP %ptr
  DMB ISH

Currently, sequences like this can not be selected with tablegen
patterns. To work around this we need to do custom selection, which has
several disadvantages compared to using patterns, such as needing
separate implementations for SelectionDAG and GlobalISel.

This patch adds basic support for tablegen Patterns which have a list
of output instructions. Pattern already has the ability to express this
but it looks like it was never implemented.

Multiple result instructions in an output pattern will be chained
together.

The GlobalISel pattern importer will skip these patterns for now. I
intend to implement this soon.

There are still some problems processing existing patterns for a few
backends. I am looking into these but don't expect them to require
major changes, and I would like feedback on the general approach of
this patch in the meantime.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D154945

Files:
  llvm/test/TableGen/dag-isel-multiple-instructions.td
  llvm/utils/TableGen/CodeGenDAGPatterns.cpp
  llvm/utils/TableGen/CodeGenDAGPatterns.h
  llvm/utils/TableGen/DAGISelEmitter.cpp
  llvm/utils/TableGen/DAGISelMatcher.cpp
  llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
  llvm/utils/TableGen/DAGISelMatcherGen.cpp
  llvm/utils/TableGen/FastISelEmitter.cpp
  llvm/utils/TableGen/GlobalISelEmitter.cpp

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