[PATCH] D154944: [ARM] Correctly handle execute-only in EmitStructByval
John Brawn via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 11 03:45:56 PDT 2023
john.brawn created this revision.
john.brawn added reviewers: stuij, simonwallis2, dmgreen.
Herald added subscribers: hiraditya, kristof.beyls.
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john.brawn requested review of this revision.
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Herald added a subscriber: llvm-commits.
Currently when compiling for an execute-only target without movt then EmitStructByval will generate a constant pool load which isn't compatible with execute-only. Handle this by emitting tMOVi32imm, and also simplify the existing movt handling by emitting t2MOVi32imm or MOVi32imm.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D154944
Files:
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/test/CodeGen/ARM/execute-only.ll
Index: llvm/test/CodeGen/ARM/execute-only.ll
===================================================================
--- llvm/test/CodeGen/ARM/execute-only.ll
+++ llvm/test/CodeGen/ARM/execute-only.ll
@@ -207,3 +207,24 @@
ret i32 2241280
}
+
+; This struct is sized so that the byval call does an inline memcpy of
+; 0x10001 bytes.
+%struct.struct_t = type { [65553 x i8] }
+ at byval_arg = global %struct.struct_t zeroinitializer
+declare void @byval_fn(ptr byval(%struct.struct_t))
+
+define void @test_byval_call() {
+entry:
+; CHECK-LABEL: test_byval_call:
+; CHECK-T2BASE: movw [[BYVAL_CPYSIZE:r[0-9]+]], #1
+; CHECK-T2: movs [[BYVAL_CPYSIZE:r[0-9]+]], #1
+; CHECK: movt [[BYVAL_CPYSIZE]], #1
+; CHECK-T1-LABEL: test_byval_call:
+; CHECK-T1: movs [[BYVAL_CPYSIZE:r[0-9]+]], #1
+; CHECK-T1: lsls [[BYVAL_CPYSIZE]], [[BYVAL_CPYSIZE]], #16
+; CHECK-T1: adds [[BYVAL_CPYSIZE]], #1
+
+ call void @byval_fn(ptr byval(%struct.struct_t) @byval_arg)
+ ret void
+}
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -11489,18 +11489,12 @@
// Load an immediate to varEnd.
Register varEnd = MRI.createVirtualRegister(TRC);
if (Subtarget->useMovt()) {
- unsigned Vtmp = varEnd;
- if ((LoopSize & 0xFFFF0000) != 0)
- Vtmp = MRI.createVirtualRegister(TRC);
- BuildMI(BB, dl, TII->get(IsThumb ? ARM::t2MOVi16 : ARM::MOVi16), Vtmp)
- .addImm(LoopSize & 0xFFFF)
- .add(predOps(ARMCC::AL));
-
- if ((LoopSize & 0xFFFF0000) != 0)
- BuildMI(BB, dl, TII->get(IsThumb ? ARM::t2MOVTi16 : ARM::MOVTi16), varEnd)
- .addReg(Vtmp)
- .addImm(LoopSize >> 16)
- .add(predOps(ARMCC::AL));
+ BuildMI(BB, dl, TII->get(IsThumb ? ARM::t2MOVi32imm : ARM::MOVi32imm),
+ varEnd)
+ .addImm(LoopSize);
+ } else if (Subtarget->genExecuteOnly()) {
+ assert(IsThumb && "Non-thumb expected to have used movt");
+ BuildMI(BB, dl, TII->get(ARM::tMOVi32imm), varEnd).addImm(LoopSize);
} else {
MachineConstantPool *ConstantPool = MF->getConstantPool();
Type *Int32Ty = Type::getInt32Ty(MF->getFunction().getContext());
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