[llvm] f0ae3c2 - [ARM] in LowerConstantFP, make sure we cover armv6-m execute-only

[Ties Stuij via llvm-commits]

Author: Ties Stuij
Date: 2023-07-11T10:42:15+01:00
New Revision: f0ae3c23b5852cb021d1c779f8884e2c94aea7a5

URL: https://github.com/llvm/llvm-project/commit/f0ae3c23b5852cb021d1c779f8884e2c94aea7a5
DIFF: https://github.com/llvm/llvm-project/commit/f0ae3c23b5852cb021d1c779f8884e2c94aea7a5.diff

LOG: [ARM] in LowerConstantFP, make sure we cover armv6-m execute-only

Currently in LowerConstantFP, when we compile for execute-only (XO) we don't
check what architecture we're compiling for (v6m=< or >v6m). We shouldn't get
here for v6m, so put in an assert.

Reviewed By: simonwallis2, dmgreen

Differential Revision: https://reviews.llvm.org/D154506

Added: 
    llvm/test/CodeGen/ARM/float-ops-xo.ll

Modified: 
    llvm/lib/Target/ARM/ARMISelLowering.cpp

Removed: 
    llvm/test/CodeGen/Thumb2/float-ops-vmovsr-nofp-xo.ll


################################################################################
diff  --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index a12fd783fb9985..7420b90ef831df 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -7070,6 +7070,10 @@ SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG,
   // Prevent floating-point constants from using literal loads
   // when execute-only is enabled.
   if (ST->genExecuteOnly()) {
+    // We shouldn't trigger this for v6m execute-only
+    assert((!ST->isThumb1Only() || ST->hasV8MBaselineOps()) &&
+           "Unexpected architecture");
+
     // If we can represent the constant as an immediate, don't lower it
     if (isFPImmLegal(FPVal, VT))
       return Op;

diff  --git a/llvm/test/CodeGen/Thumb2/float-ops-vmovsr-nofp-xo.ll b/llvm/test/CodeGen/ARM/float-ops-xo.ll
similarity index 59%
rename from llvm/test/CodeGen/Thumb2/float-ops-vmovsr-nofp-xo.ll
rename to llvm/test/CodeGen/ARM/float-ops-xo.ll
index a71cd44063ae7e..6ff85ad0b6f767 100644
--- a/llvm/test/CodeGen/Thumb2/float-ops-vmovsr-nofp-xo.ll
+++ b/llvm/test/CodeGen/ARM/float-ops-xo.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc < %s -mtriple=thumbv8.1m.main-none-eabihf -mattr=+mve,+execute-only | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv6m -mattr=+execute-only | FileCheck %s --check-prefix=V6M
 
 declare void @ext_fn(float)
 
@@ -12,6 +13,13 @@ define void @test1() {
 ; CHECK-NEXT:    vmov s0, r0
 ; CHECK-NEXT:    bl ext_fn
 ; CHECK-NEXT:    pop {r7, pc}
+;
+; V6M-LABEL: test1:
+; V6M:       @ %bb.0: @ %entry
+; V6M-NEXT:    push {r7, lr}
+; V6M-NEXT:    movs r0, #0
+; V6M-NEXT:    bl ext_fn
+; V6M-NEXT:    pop {r7, pc}
 entry:
   call void @ext_fn(float 0.000000e+00)
   ret void
@@ -24,6 +32,17 @@ define float @test2() {
 ; CHECK-NEXT:    movt r0, #16673
 ; CHECK-NEXT:    vmov s0, r0
 ; CHECK-NEXT:    bx lr
+;
+; V6M-LABEL: test2:
+; V6M:       @ %bb.0: @ %entry
+; V6M-NEXT:    movs r0, #65
+; V6M-NEXT:    lsls r0, r0, #8
+; V6M-NEXT:    adds r0, #33
+; V6M-NEXT:    lsls r0, r0, #8
+; V6M-NEXT:    adds r0, #249
+; V6M-NEXT:    lsls r0, r0, #8
+; V6M-NEXT:    adds r0, #167
+; V6M-NEXT:    bx lr
 entry:
   ret float 0x40243F34E0000000
 }