[PATCH] D153850: [AArch64] Use GlobalISel MatchTable Combiner Backend

[Pierre van Houtryve via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG655714a300ff: [AArch64] Use GlobalISel MatchTable Combiner Backend (authored by Pierre-vh).

Changed prior to commit:
  https://reviews.llvm.org/D153850?vs=537266&id=538979#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153850/new/

https://reviews.llvm.org/D153850

Files:
  llvm/lib/Target/AArch64/AArch64Combine.td
  llvm/lib/Target/AArch64/CMakeLists.txt
  llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp
  llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
  llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
  llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/combine-and-or-disjoint-mask.mir
  llvm/test/CodeGen/AArch64/GlobalISel/combine-icmp-to-lhs-known-bits.mir
  llvm/test/CodeGen/AArch64/GlobalISel/combine-mulo-with-2.mir
  llvm/test/CodeGen/AArch64/GlobalISel/combine-select.mir
  llvm/test/CodeGen/AArch64/GlobalISel/form-bitfield-extract-from-and.mir
  llvm/test/CodeGen/AArch64/GlobalISel/lower-neon-vector-fcmp.mir
  llvm/test/CodeGen/AArch64/GlobalISel/opt-overlapping-and-postlegalize.mir
  llvm/test/CodeGen/AArch64/GlobalISel/opt-overlapping-and.mir
  llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combine-ptr-add-chain.mir
  llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-anyext-to-zext.mir
  llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuf-to-ins.mir
  llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-rotate.mir
  llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-addo-zero.mir
  llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-icmp-to-true-false-known-bits.mir
  llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-and-mask.mir
  llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-or-pattern-align.mir
  llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-or-pattern.mir
  llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-mulo-zero.mir
  llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-br.mir
  llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-copy-prop-disabled.mir
  llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-invert-cmp.mir

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