[PATCH] D153748: [RISCV] Add support for XCValu extension in CV32E40P

[QIHAN CAI via Phabricator via llvm-commits]

realqhc updated this revision to Diff 538967.
realqhc added a comment.

fix previous errorneus update


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153748/new/

https://reviews.llvm.org/D153748

Files:
  llvm/docs/RISCVUsage.rst
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
  llvm/test/MC/RISCV/corev/XCValu-invalid.s
  llvm/test/MC/RISCV/corev/XCValu-valid.s

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D153748.538967.patch
Type: text/x-patch
Size: 40098 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230711/0e87e353/attachment.bin>