[llvm] e148899 - [X86] Preserve volatile ATOMIC_LOAD_OR nodes

[Nabeel Omer via llvm-commits]

Author: Nabeel Omer
Date: 2023-07-11T08:05:38Z
New Revision: e148899ad9f384e77e1440f6cf8b03f5fbbc11d2

URL: https://github.com/llvm/llvm-project/commit/e148899ad9f384e77e1440f6cf8b03f5fbbc11d2
DIFF: https://github.com/llvm/llvm-project/commit/e148899ad9f384e77e1440f6cf8b03f5fbbc11d2.diff

LOG: [X86] Preserve volatile ATOMIC_LOAD_OR nodes

Fixes #63692.

In reference to volatile memory accesses, the langref says:
> the backend should never split or merge target-legal volatile load/store instructions.

Differential Revision: https://reviews.llvm.org/D154609

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp
    llvm/test/CodeGen/X86/pr63692.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 74bd1d817e6f01..bf8acd38eaea2a 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -33552,7 +33552,9 @@ static SDValue lowerAtomicArith(SDValue N, SelectionDAG &DAG,
   // changing, all we need is a lowering for the *ordering* impacts of the
   // atomicrmw.  As such, we can chose a 
diff erent operation and memory
   // location to minimize impact on other code.
-  if (Opc == ISD::ATOMIC_LOAD_OR && isNullConstant(RHS)) {
+  // The above holds unless the node is marked volatile in which
+  // case it needs to be preserved according to the langref.
+  if (Opc == ISD::ATOMIC_LOAD_OR && isNullConstant(RHS) && !AN->isVolatile()) {
     // On X86, the only ordering which actually requires an instruction is
     // seq_cst which isn't SingleThread, everything just needs to be preserved
     // during codegen and then dropped. Note that we expect (but don't assume),

diff  --git a/llvm/test/CodeGen/X86/pr63692.ll b/llvm/test/CodeGen/X86/pr63692.ll
index 30e13043643102..fb3198743a3949 100644
--- a/llvm/test/CodeGen/X86/pr63692.ll
+++ b/llvm/test/CodeGen/X86/pr63692.ll
@@ -9,7 +9,7 @@ define void @prefault(ptr noundef %range_start, ptr noundef readnone %range_end)
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  .LBB0_1: # %while.body
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    #MEMBARRIER
+; CHECK-NEXT:    lock orb $0, (%rdi)
 ; CHECK-NEXT:    addq $4096, %rdi # imm = 0x1000
 ; CHECK-NEXT:    cmpq %rsi, %rdi
 ; CHECK-NEXT:    jb .LBB0_1