[PATCH] D154819: [LoongArch] Implement isZextFree

[hev via Phabricator via llvm-commits]

hev added inline comments.


================
Comment at: llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp:3256
+  // Zexts are free if they can be combined with a load.
+  // Don't advertise i32->i64 zextload as being free for LA64. It interacts
+  // poorly with type legalization of compares preferring sext.
----------------
SixWeining wrote:
> I'm not sure why we cannot do this. But seems that RISCV is the same.
There is no register width in LoongArch's instruction encoding, and the results of most 32-bit (W) instructions are sign-extended to 64-bit registers. Zero-extended values have additional overhead as input to the W instruction.


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  https://reviews.llvm.org/D154819/new/

https://reviews.llvm.org/D154819