[PATCH] D154920: [RISCV] Contrain register class before replaceRegWith in RISCVMergeBaseOffset.

[Craig Topper via Phabricator via llvm-commits]

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The register being replaced might have a more restrictive register
class due to requirements of the using instruction. We should
constrain the register class to preserve any restrictions.

This was found in our downstream on a custom instruction. I don't
have a test case for upstream currently.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D154920

Files:
  llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp


Index: llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+++ llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
@@ -140,6 +140,8 @@
   if (Hi.getOpcode() != RISCV::AUIPC)
     Lo.getOperand(2).setOffset(Offset);
   // Delete the tail instruction.
+  MRI->constrainRegClass(Lo.getOperand(0).getReg(),
+                         MRI->getRegClass(Tail.getOperand(0).getReg()));
   MRI->replaceRegWith(Tail.getOperand(0).getReg(), Lo.getOperand(0).getReg());
   Tail.eraseFromParent();
   LLVM_DEBUG(dbgs() << "  Merged offset " << Offset << " into base.\n"


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