[PATCH] D154635: [7/8][RISCV] Add rounding mode control variant for conversion intrinsics between floating-point and integer
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 10 13:55:43 PDT 2023
craig.topper added inline comments.
================
Comment at: llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll:24
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
----------------
This is concerning. This means the `vfcvt.f.x.v` is getting the modified rounding mode from `fsrmi a0, 3`. I think its functionally ok due to the inputs involved, but it still shouldn't be happening. Is the vfcvt.f.x.v missing its FRM implicit dependency for DYN?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D154635/new/
https://reviews.llvm.org/D154635
More information about the llvm-commits
mailing list