[PATCH] D148762: [RISCV] Rename some tablegen variables to improve code clarity in the vector load/store instruction definitions

Michael Maitland via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Jul 10 09:48:53 PDT 2023

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michaelmaitland closed this revision.
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  https://reviews.llvm.org/D148762/new/

https://reviews.llvm.org/D148762

Previous message: [PATCH] D144925: [RISCV][NFC] Replace the pseudos for instructions that depend on lmul with variants that encode the SEW into the name
Next message: [PATCH] D147740: [llvm-profdata] Refactoring Sample Profile Reader to increase FDO build speed using MD5 as key to Sample Profile map
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