[PATCH] D154845: [ARM] mark tMOVi32imm as killing flags

[Simon Wallis via Phabricator via llvm-commits]

simonwallis2 created this revision.
simonwallis2 added reviewers: stuij, john.brawn, olista01, keith.walker.arm.
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Mark the tMOVi32imm pseudo instr as killing the flags register.

The pseudo instruction expands to a sequence of 7 movs/lsls/adds
instructions, which are all Thumb-1 flag setting instructions.

For a test case, take an existing arm test which checks for
"Don't CSE a cmp across a call that clobbers CPSR."
and retarget it at thumbv6m execute-only.


https://reviews.llvm.org/D154845

Files:
  llvm/lib/Target/ARM/ARMInstrThumb.td
  llvm/test/CodeGen/ARM/cse-call.ll
  llvm/test/CodeGen/ARM/udivmodei5.ll


Index: llvm/test/CodeGen/ARM/udivmodei5.ll
===================================================================
--- llvm/test/CodeGen/ARM/udivmodei5.ll
+++ llvm/test/CodeGen/ARM/udivmodei5.ll
@@ -1,4 +1,5 @@
 ; RUN: llc -mtriple=arm-eabi < %s | FileCheck %s
+; RUN: llc -mtriple=thumbv6m-eabi -mattr=+execute-only -verify-machineinstrs < %s | FileCheck %s
 
 define i65 @udiv65(i65 %a, i65 %b) nounwind {
 ; CHECK-LABEL: udiv65:
Index: llvm/test/CodeGen/ARM/cse-call.ll
===================================================================
--- llvm/test/CodeGen/ARM/cse-call.ll
+++ llvm/test/CodeGen/ARM/cse-call.ll
@@ -1,10 +1,29 @@
-; RUN: llc < %s -mcpu=arm1136jf-s -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=armv6-apple-ios0.0.0 -mcpu=arm1136jf-s -verify-machineinstrs | FileCheck %s
+; RUN: llc -mtriple=thumbv6m-eabi -mattr=+execute-only -verify-machineinstrs %s -o - | FileCheck --check-prefix=CHECK-T1 %s
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
-target triple = "armv6-apple-ios0.0.0"
 
 ; Don't CSE a cmp across a call that clobbers CPSR.
 ;
 ; CHECK: cmp
+
+; CHECK-T1: movs [[REG:r[0-7]+]], :upper8_15:
+; CHECK-T1-NEXT: lsls    [[REG]], [[REG]], #8
+; CHECK-T1-NEXT: adds    [[REG]], :upper0_7:
+; CHECK-T1-NEXT: lsls    [[REG]], [[REG]], #8
+; CHECK-T1-NEXT: adds    [[REG]], :lower8_15:
+; CHECK-T1-NEXT: lsls    [[REG]], [[REG]], #8
+; CHECK-T1-NEXT: adds    [[REG]], :lower0_7:
+
+; CHECK-T1: movs [[REG:r[0-7]+]], :upper8_15:
+; CHECK-T1-NEXT: lsls    [[REG]], [[REG]], #8
+; CHECK-T1-NEXT: adds    [[REG]], :upper0_7:
+; CHECK-T1-NEXT: lsls    [[REG]], [[REG]], #8
+; CHECK-T1-NEXT: adds    [[REG]], :lower8_15:
+; CHECK-T1-NEXT: lsls    [[REG]], [[REG]], #8
+; CHECK-T1-NEXT: adds    [[REG]], :lower0_7:
+
+; CHECK-T1: cmp
+
 ; CHECK: S_trimzeros
 ; CHECK: cmp
 ; CHECK: strlen
Index: llvm/lib/Target/ARM/ARMInstrThumb.td
===================================================================
--- llvm/lib/Target/ARM/ARMInstrThumb.td
+++ llvm/lib/Target/ARM/ARMInstrThumb.td
@@ -1609,7 +1609,7 @@
 // relocations.
 // This is a single pseudo instruction to make it re-materializable.
 // FIXME: Remove this when we can do generalized remat.
-let isReMaterializable = 1, isMoveImm = 1, Size = 16, hasNoSchedulingInfo = 1 in
+let Defs = [CPSR], isReMaterializable = 1, isMoveImm = 1, Size = 16, hasNoSchedulingInfo = 1 in
 def tMOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), NoItinerary,
                             [(set rGPR:$dst, (i32 imm:$src))]>,
                             Requires<[IsThumb1Only, GenExecuteOnly, DontUseMovt]>;


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