[llvm] 4a5b5bf - [AArch64] Remove duplicate code (NFC)
Evandro Menezes via llvm-commits
llvm-commits at lists.llvm.org
Sat Jul 1 11:30:56 PDT 2023
Author: Evandro Menezes
Date: 2023-07-01T13:29:55-05:00
New Revision: 4a5b5bf318a858e07d1916e798adc2a1aebd56d3
URL: https://github.com/llvm/llvm-project/commit/4a5b5bf318a858e07d1916e798adc2a1aebd56d3
DIFF: https://github.com/llvm/llvm-project/commit/4a5b5bf318a858e07d1916e798adc2a1aebd56d3.diff
LOG: [AArch64] Remove duplicate code (NFC)
Remove multiple versions of the predicate that checks if the
instruction operand is shifted by up to 4.
Added:
Modified:
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64SchedAmpere1.td
llvm/lib/Target/AArch64/AArch64SchedNeoverseN1.td
llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td
llvm/lib/Target/AArch64/AArch64SchedPredicates.td
Removed:
llvm/lib/Target/AArch64/AArch64SchedPredAmpere.td
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index 4d9745655c614..1a87e9b9d989b 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -671,7 +671,6 @@ include "AArch64Schedule.td"
include "AArch64InstrInfo.td"
include "AArch64SchedPredicates.td"
include "AArch64SchedPredExynos.td"
-include "AArch64SchedPredAmpere.td"
include "AArch64SchedPredNeoverse.td"
include "AArch64Combine.td"
diff --git a/llvm/lib/Target/AArch64/AArch64SchedAmpere1.td b/llvm/lib/Target/AArch64/AArch64SchedAmpere1.td
index b8d5a70d7ec64..de09177d1dc06 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedAmpere1.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedAmpere1.td
@@ -571,12 +571,12 @@ def Ampere1Write_62cyc_1XY : SchedWriteRes<[Ampere1UnitXY]> {
// across Unit A or B for both uops.
def Ampere1Write_Arith : SchedWriteVariant<[
SchedVar<RegExtendedPred, [Ampere1Write_2cyc_2AB]>,
- SchedVar<AmpereCheapLSL, [Ampere1Write_1cyc_1AB]>,
+ SchedVar<IsCheapLSL, [Ampere1Write_1cyc_1AB]>,
SchedVar<NoSchedPred, [Ampere1Write_2cyc_1B_1AB]>]>;
def Ampere1Write_ArithFlagsetting : SchedWriteVariant<[
SchedVar<RegExtendedPred, [Ampere1Write_2cyc_1AB_1A]>,
- SchedVar<AmpereCheapLSL, [Ampere1Write_1cyc_1A]>,
+ SchedVar<IsCheapLSL, [Ampere1Write_1cyc_1A]>,
SchedVar<NoSchedPred, [Ampere1Write_2cyc_1B_1A]>]>;
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN1.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN1.td
index dc7580d712b54..d689b9fa9c068 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN1.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN1.td
@@ -309,8 +309,8 @@ def : SchedAlias<WriteIEReg, N1Write_2c_1M>;
// Arithmetic, flagset, LSL shift, shift <= 4
// Arithmetic, LSR/ASR/ROR shift or LSL shift > 4
def N1WriteISReg : SchedWriteVariant<[
- SchedVar<NeoverseCheapLSL, [N1Write_1c_1I]>,
- SchedVar<NoSchedPred, [N1Write_2c_1M]>]>;
+ SchedVar<IsCheapLSL, [N1Write_1c_1I]>,
+ SchedVar<NoSchedPred, [N1Write_2c_1M]>]>;
def : SchedAlias<WriteISReg, N1WriteISReg>;
// Logical, shift, no flagset
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
index ee5c9280095f6..6bb71f2ce2360 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
@@ -612,8 +612,8 @@ def N2Write_11cyc_9L01_9S_9V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01,
//===----------------------------------------------------------------------===//
// Define types for arithmetic and logical ops with short shifts
def N2Write_Arith : SchedWriteVariant<[
- SchedVar<NeoverseCheapLSL, [N2Write_1cyc_1I]>,
- SchedVar<NoSchedPred, [N2Write_2cyc_1M]>]>;
+ SchedVar<IsCheapLSL, [N2Write_1cyc_1I]>,
+ SchedVar<NoSchedPred, [N2Write_2cyc_1M]>]>;
def N2Write_Logical: SchedWriteVariant<[
SchedVar<NeoverseNoLSL, [N2Write_1cyc_1I]>,
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
index 73314139f25f6..30bb3562d43c6 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
@@ -877,12 +877,12 @@ def V2Write_11cyc_18L01_18S_18V01 : SchedWriteRes<[V2UnitL01, V2UnitL01,
// Define predicate-controlled types
def V2Write_ArithI : SchedWriteVariant<[
- SchedVar<NeoverseCheapLSL, [V2Write_1cyc_1I]>,
- SchedVar<NoSchedPred, [V2Write_2cyc_1M]>]>;
+ SchedVar<IsCheapLSL, [V2Write_1cyc_1I]>,
+ SchedVar<NoSchedPred, [V2Write_2cyc_1M]>]>;
def V2Write_ArithF : SchedWriteVariant<[
- SchedVar<NeoverseCheapLSL, [V2Write_1cyc_1F]>,
- SchedVar<NoSchedPred, [V2Write_2cyc_1M]>]>;
+ SchedVar<IsCheapLSL, [V2Write_1cyc_1F]>,
+ SchedVar<NoSchedPred, [V2Write_2cyc_1M]>]>;
def V2Write_Logical : SchedWriteVariant<[
SchedVar<NeoverseNoLSL, [V2Write_1cyc_1F]>,
diff --git a/llvm/lib/Target/AArch64/AArch64SchedPredAmpere.td b/llvm/lib/Target/AArch64/AArch64SchedPredAmpere.td
deleted file mode 100644
index 8552c07bda568..0000000000000
--- a/llvm/lib/Target/AArch64/AArch64SchedPredAmpere.td
+++ /dev/null
@@ -1,25 +0,0 @@
-//===- AArch64SchedPredAmpere.td - AArch64 Sched Preds -----*- tablegen -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This file defines scheduling predicate definitions that are used by the
-// AArch64 Ampere Computing processors.
-//
-//===----------------------------------------------------------------------===//
-
-// Auxiliary predicates.
-
-// Check for a LSL shift <= 4
-def AmpereCheapLSL : MCSchedPredicate<
- CheckAny<[CheckShiftBy0,
- CheckAll<
- [CheckShiftLSL,
- CheckAny<
- [CheckShiftBy1,
- CheckShiftBy2,
- CheckShiftBy3,
- CheckShiftBy4]>]>]>>;
diff --git a/llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td b/llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td
index 1eb5cee5060cd..8785b47994267 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td
@@ -13,17 +13,6 @@
// Auxiliary predicates.
-// Check for LSL shift <= 4
-def NeoverseCheapLSL : MCSchedPredicate<
- CheckAll<
- [CheckShiftLSL,
- CheckAny<
- [CheckShiftBy0,
- CheckShiftBy1,
- CheckShiftBy2,
- CheckShiftBy3,
- CheckShiftBy4]>]>>;
-
// Check for LSL shift == 0
def NeoverseNoLSL : MCSchedPredicate<
CheckAll<[CheckShiftLSL,
diff --git a/llvm/lib/Target/AArch64/AArch64SchedPredicates.td b/llvm/lib/Target/AArch64/AArch64SchedPredicates.td
index e9b66cd22cc98..355e35130a97d 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedPredicates.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedPredicates.td
@@ -31,6 +31,12 @@ foreach I = {0-3} in {
def CheckExtBy#I : CheckImmOperand<3, I>;
}
+// Check for shifting in arithmetic and logic instructions.
+foreach I = {0-4, 8} in {
+ let FunctionMapper = "AArch64_AM::getShiftValue" in
+ def CheckShiftBy#I : CheckImmOperand<3, I>;
+}
+
// Check the extension type in the register offset addressing mode.
let FunctionMapper = "AArch64_AM::getMemExtendType" in {
def CheckMemExtUXTW : CheckImmOperand_s<3, "AArch64_AM::UXTW">;
@@ -52,12 +58,6 @@ let FunctionMapper = "AArch64_AM::getShiftType" in {
def CheckShiftMSL : CheckImmOperand_s<3, "AArch64_AM::MSL">;
}
-// Check for shifting in arithmetic and logic instructions.
-foreach I = {0-4, 8} in {
- let FunctionMapper = "AArch64_AM::getShiftValue" in
- def CheckShiftBy#I : CheckImmOperand<3, I>;
-}
-
// Generic predicates.
// Identify whether an instruction is NEON or floating point
def CheckFpOrNEON : CheckFunctionPredicateWithTII<
@@ -218,38 +218,6 @@ def IsLoadStoreRegOffsetOp : CheckOpcode<!listconcat(IsLoadRegOffsetOp.ValidOpco
// Target predicates.
-// Identify an instruction that effectively transfers a register to another.
-def IsCopyIdiomFn : TIIPredicate<"isCopyIdiom",
- MCOpcodeSwitchStatement<
- [// MOV {Rd, SP}, {SP, Rn} =>
- // ADD {Rd, SP}, {SP, Rn}, #0
- MCOpcodeSwitchCase<
- [ADDWri, ADDXri],
- MCReturnStatement<
- CheckAll<
- [CheckIsRegOperand<0>,
- CheckIsRegOperand<1>,
- CheckAny<
- [CheckRegOperand<0, WSP>,
- CheckRegOperand<0, SP>,
- CheckRegOperand<1, WSP>,
- CheckRegOperand<1, SP>]>,
- CheckZeroOperand<2>]>>>,
- // MOV Rd, Rm =>
- // ORR Rd, ZR, Rm, LSL #0
- MCOpcodeSwitchCase<
- [ORRWrs, ORRXrs],
- MCReturnStatement<
- CheckAll<
- [CheckIsRegOperand<1>,
- CheckIsRegOperand<2>,
- CheckAny<
- [CheckRegOperand<1, WZR>,
- CheckRegOperand<1, XZR>]>,
- CheckShiftBy0]>>>],
- MCReturnStatement<FalsePred>>>;
-def IsCopyIdiomPred : MCSchedPredicate<IsCopyIdiomFn>;
-
// Identify arithmetic instructions with an extended register.
def RegExtendedFn : TIIPredicate<"hasExtendedReg",
MCOpcodeSwitchStatement<
@@ -282,24 +250,52 @@ def ScaledIdxFn : TIIPredicate<"isScaledAddr",
MCReturnStatement<FalsePred>>>;
def ScaledIdxPred : MCSchedPredicate<ScaledIdxFn>;
-// Identify an instruction that effectively resets a FP register to zero.
-def IsZeroFPIdiomFn : TIIPredicate<"isZeroFPIdiom",
+// Special cases.
+
+// Check for LSL shift <= 4
+def IsCheapLSL : MCSchedPredicate<
+ CheckAll<
+ [CheckShiftLSL,
+ CheckAny<
+ [CheckShiftBy0,
+ CheckShiftBy1,
+ CheckShiftBy2,
+ CheckShiftBy3,
+ CheckShiftBy4]>]>>;
+
+// Idioms.
+
+// Identify an instruction that effectively transfers a register to another.
+def IsCopyIdiomFn : TIIPredicate<"isCopyIdiom",
MCOpcodeSwitchStatement<
- [// MOVI Vd, #0
+ [// MOV {Rd, SP}, {SP, Rn} =>
+ // ADD {Rd, SP}, {SP, Rn}, #0
MCOpcodeSwitchCase<
- [MOVIv8b_ns, MOVIv16b_ns,
- MOVID, MOVIv2d_ns],
- MCReturnStatement<CheckZeroOperand<1>>>,
- // MOVI Vd, #0, LSL #0
+ [ADDWri, ADDXri],
+ MCReturnStatement<
+ CheckAll<
+ [CheckIsRegOperand<0>,
+ CheckIsRegOperand<1>,
+ CheckAny<
+ [CheckRegOperand<0, WSP>,
+ CheckRegOperand<0, SP>,
+ CheckRegOperand<1, WSP>,
+ CheckRegOperand<1, SP>]>,
+ CheckZeroOperand<2>]>>>,
+ // MOV Rd, Rm =>
+ // ORR Rd, ZR, Rm, LSL #0
MCOpcodeSwitchCase<
- [MOVIv4i16, MOVIv8i16,
- MOVIv2i32, MOVIv4i32],
+ [ORRWrs, ORRXrs],
MCReturnStatement<
CheckAll<
- [CheckZeroOperand<1>,
- CheckZeroOperand<2>]>>>],
+ [CheckIsRegOperand<1>,
+ CheckIsRegOperand<2>,
+ CheckAny<
+ [CheckRegOperand<1, WZR>,
+ CheckRegOperand<1, XZR>]>,
+ CheckShiftBy0]>>>],
MCReturnStatement<FalsePred>>>;
-def IsZeroFPIdiomPred : MCSchedPredicate<IsZeroFPIdiomFn>;
+def IsCopyIdiomPred : MCSchedPredicate<IsCopyIdiomFn>;
// Identify an instruction that effectively resets a GP register to zero.
def IsZeroIdiomFn : TIIPredicate<"isZeroIdiom",
@@ -317,6 +313,25 @@ def IsZeroIdiomFn : TIIPredicate<"isZeroIdiom",
MCReturnStatement<FalsePred>>>;
def IsZeroIdiomPred : MCSchedPredicate<IsZeroIdiomFn>;
+// Identify an instruction that effectively resets a FP register to zero.
+def IsZeroFPIdiomFn : TIIPredicate<"isZeroFPIdiom",
+ MCOpcodeSwitchStatement<
+ [// MOVI Vd, #0
+ MCOpcodeSwitchCase<
+ [MOVIv8b_ns, MOVIv16b_ns,
+ MOVID, MOVIv2d_ns],
+ MCReturnStatement<CheckZeroOperand<1>>>,
+ // MOVI Vd, #0, LSL #0
+ MCOpcodeSwitchCase<
+ [MOVIv4i16, MOVIv8i16,
+ MOVIv2i32, MOVIv4i32],
+ MCReturnStatement<
+ CheckAll<
+ [CheckZeroOperand<1>,
+ CheckZeroOperand<2>]>>>],
+ MCReturnStatement<FalsePred>>>;
+def IsZeroFPIdiomPred : MCSchedPredicate<IsZeroFPIdiomFn>;
+
// Identify EXTR as the alias for ROR (immediate).
def IsRORImmIdiomPred : MCSchedPredicate<
CheckAll<[CheckOpcode<[EXTRWrri, EXTRXrri]>,
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