[llvm] afb2743 - [AArch64] Remove duplicate code (NFC)

[Evandro Menezes via llvm-commits]

Author: Evandro Menezes
Date: 2023-06-30T21:37:51-05:00
New Revision: afb2743778689b585ce5539ee352e65a918835e2

URL: https://github.com/llvm/llvm-project/commit/afb2743778689b585ce5539ee352e65a918835e2
DIFF: https://github.com/llvm/llvm-project/commit/afb2743778689b585ce5539ee352e65a918835e2.diff

LOG: [AArch64] Remove duplicate code (NFC)

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
    llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
index 607856457820bb..73314139f25f65 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
@@ -889,8 +889,8 @@ def V2Write_Logical : SchedWriteVariant<[
                         SchedVar<NoSchedPred,   [V2Write_2cyc_1M]>]>;
 
 def V2Write_Extr : SchedWriteVariant<[
-                     SchedVar<NeoverseOneRegEXTR,  [V2Write_1cyc_1I]>,
-                     SchedVar<NoSchedPred,         [V2Write_3cyc_1I_1M]>]>;
+                     SchedVar<IsRORImmIdiomPred, [V2Write_1cyc_1I]>,
+                     SchedVar<NoSchedPred,       [V2Write_3cyc_1I_1M]>]>;
 
 def V2Write_LdrHQ : SchedWriteVariant<[
                       SchedVar<NeoverseHQForm,  [V2Write_7cyc_1I_1L]>,

diff  --git a/llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td b/llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td
index 6c705d70c6253b..1eb5cee5060cdf 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td
@@ -37,11 +37,6 @@ def NeoverseReg3IsZero : MCSchedPredicate<
                                 [CheckRegOperand<3, WZR>,
                                  CheckRegOperand<3, XZR>]>]>>;
 
-// Identify EXTR with one register (alias for ROR immediate)
-def NeoverseOneRegEXTR : MCSchedPredicate<
-                           CheckAll<[CheckOpcode<[EXTRWrri, EXTRXrri]>,
-                                     CheckSameRegOperand<1, 2>]>>;
-
 // Identify LDR/STR H/Q-form scaled (and potentially extended) FP instructions
 def NeoverseHQForm : MCSchedPredicate<
                        CheckAll<[