[llvm] 9d8171f - [AMDGPU][Codegen] Clean up legalizeOpWithMove().

[Ivan Kosarev via llvm-commits]

Author: Ivan Kosarev
Date: 2023-06-30T16:48:16+01:00
New Revision: 9d8171f8c49dc9b2d49a38d46a6da8dfb5e7c672

URL: https://github.com/llvm/llvm-project/commit/9d8171f8c49dc9b2d49a38d46a6da8dfb5e7c672
DIFF: https://github.com/llvm/llvm-project/commit/9d8171f8c49dc9b2d49a38d46a6da8dfb5e7c672.diff

LOG: [AMDGPU][Codegen] Clean up legalizeOpWithMove().

The removed logic was added in
<https://reviews.llvm.org/rG0c93c9ecee0624f8469f5a971a09fbc9e9cc1061>,
but now doesn't seem to be needed.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D154220

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index bcb27826a2675..1babd9cd2d696 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -5022,12 +5022,6 @@ void SIInstrInfo::legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const {
     Opcode = (Size == 64) ? AMDGPU::S_MOV_B64 : AMDGPU::S_MOV_B32;
 
   const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
-  const TargetRegisterClass *VRC64 = RI.getVGPR64Class();
-  if (RI.getCommonSubClass(VRC64, VRC))
-    VRC = VRC64;
-  else
-    VRC = &AMDGPU::VGPR_32RegClass;
-
   Register Reg = MRI.createVirtualRegister(VRC);
   DebugLoc DL = MBB->findDebugLoc(I);
   BuildMI(*MI.getParent(), I, DL, get(Opcode), Reg).add(MO);