[PATCH] D154220: [AMDGPU][Codegen] Clean up legalizeOpWithMove().

Ivan Kosarev via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Jun 30 07:09:45 PDT 2023


kosarev created this revision.
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The removed logic was added in
https://reviews.llvm.org/rG0c93c9ecee0624f8469f5a971a09fbc9e9cc1061,
but now doesn't seem to be needed.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D154220

Files:
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp


Index: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -5022,12 +5022,6 @@
     Opcode = (Size == 64) ? AMDGPU::S_MOV_B64 : AMDGPU::S_MOV_B32;
 
   const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
-  const TargetRegisterClass *VRC64 = RI.getVGPR64Class();
-  if (RI.getCommonSubClass(VRC64, VRC))
-    VRC = VRC64;
-  else
-    VRC = &AMDGPU::VGPR_32RegClass;
-
   Register Reg = MRI.createVirtualRegister(VRC);
   DebugLoc DL = MBB->findDebugLoc(I);
   BuildMI(*MI.getParent(), I, DL, get(Opcode), Reg).add(MO);


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