[PATCH] D154213: [X86][FP16] Fix mis-combination from FMULC to FCMULC
Phoebe Wang via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 30 06:15:33 PDT 2023
pengfei created this revision.
pengfei added reviewers: RKSimon, FreddyYe, LuoYuanke, craig.topper.
Herald added a subscriber: hiraditya.
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pengfei requested review of this revision.
Herald added a project: LLVM.
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The combination was designed to combine a negative imaginary value
rather then a full negative complex value.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D154213
Files:
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/avx512fp16-combine-xor-vfmulc.ll
Index: llvm/test/CodeGen/X86/avx512fp16-combine-xor-vfmulc.ll
===================================================================
--- llvm/test/CodeGen/X86/avx512fp16-combine-xor-vfmulc.ll
+++ llvm/test/CodeGen/X86/avx512fp16-combine-xor-vfmulc.ll
@@ -69,8 +69,10 @@
define dso_local <32 x half> @test5(<32 x half> noundef %a, <32 x half> noundef %b) local_unnamed_addr #0 {
; CHECK-LABEL: test5:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vfcmulcph %zmm1, %zmm0, %zmm2
-; CHECK-NEXT: vmovaps %zmm2, %zmm0
+; CHECK-NEXT: vpbroadcastw {{.*#+}} zmm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
+; CHECK-NEXT: vpxorq %zmm2, %zmm1, %zmm2
+; CHECK-NEXT: vfmulcph %zmm2, %zmm0, %zmm1
+; CHECK-NEXT: vmovaps %zmm1, %zmm0
; CHECK-NEXT: retq
entry:
%fneg = fneg <32 x half> %b
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- llvm/lib/Target/X86/X86ISelLowering.cpp
+++ llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -52865,7 +52865,7 @@
}
}
if (const auto *CF = dyn_cast<ConstantFP>(c))
- return CF->isNegativeZeroValue();
+ return CF->getType()->isFloatTy() && CF->isNegativeZeroValue();
return false;
};
auto combineConjugation = [&](SDValue &r) {
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