[llvm] 2086801 - [LoongArch] Reuse LoongArchRegWithSubRegs class to shorten some code in LoongArchRegisterInfo.td. NFC

[via llvm-commits]

Author: wanglei
Date: 2023-06-30T11:07:28+08:00
New Revision: 2086801a9aacfa106644779f9ac550644891387c

URL: https://github.com/llvm/llvm-project/commit/2086801a9aacfa106644779f9ac550644891387c
DIFF: https://github.com/llvm/llvm-project/commit/2086801a9aacfa106644779f9ac550644891387c.diff

LOG: [LoongArch] Reuse LoongArchRegWithSubRegs class to shorten some code in LoongArchRegisterInfo.td. NFC

Added: 
    

Modified: 
    llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td

Removed: 
    


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diff  --git a/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td b/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td
index ff914f805e5b2f..b34e03367cba8e 100644
--- a/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td
@@ -17,6 +17,13 @@ class LoongArchReg<bits<16> Enc, string n, list<string> alt = []>
   let AltNames = alt;
 }
 
+class LoongArchRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs,
+                              list<string> alt = []>
+    : RegisterWithSubRegs<n, subregs> {
+  let HWEncoding = Enc;
+  let AltNames = alt;
+}
+
 class LoongArchReg32<bits<16> Enc, string n, list<string> alt = []>
     : Register<n> {
   let HWEncoding = Enc;
@@ -25,12 +32,9 @@ class LoongArchReg32<bits<16> Enc, string n, list<string> alt = []>
 
 def sub_32 : SubRegIndex<32>;
 class LoongArchReg64<LoongArchReg32 subreg>
-    : Register<""> {
-  let HWEncoding = subreg.HWEncoding;
-  let SubRegs = [subreg];
+    : LoongArchRegWithSubRegs<subreg.HWEncoding, subreg.AsmName, [subreg],
+                              subreg.AltNames> {
   let SubRegIndices = [sub_32];
-  let AsmName = subreg.AsmName;
-  let AltNames = subreg.AltNames;
 }
 
 let FallbackRegAltNameIndex = NoRegAltName in