[llvm] 096b6b4 - [RISCV][NFC] Format TableGen files and remove unused defs
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 29 20:00:26 PDT 2023
Author: wangpc
Date: 2023-06-30T10:59:05+08:00
New Revision: 096b6b4f42e1d29f40419eee3cd55d924f29ab7e
URL: https://github.com/llvm/llvm-project/commit/096b6b4f42e1d29f40419eee3cd55d924f29ab7e
DIFF: https://github.com/llvm/llvm-project/commit/096b6b4f42e1d29f40419eee3cd55d924f29ab7e.diff
LOG: [RISCV][NFC] Format TableGen files and remove unused defs
Make sure there is no single line for '{' to be consistent with
other codes.
`InvalidIndex` is removed since it's unused now. And comments are
updated.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D153939
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoC.td
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
index 22acb94ef26f4..bf87bc41e74f4 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -401,8 +401,7 @@ def C_SD : CStore_rri<0b111, "c.sd", GPRC, uimm8_lsb000>,
let rd = 0, imm = 0, hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
def C_NOP : RVInst16CI<0b000, 0b01, (outs), (ins), "c.nop", "">,
- Sched<[WriteNop]>
-{
+ Sched<[WriteNop]> {
let Inst{6-2} = 0;
}
@@ -622,8 +621,7 @@ def C_UNIMP : RVInst16<(outs), (ins), "c.unimp", "", [], InstFormatOther>,
//===----------------------------------------------------------------------===//
let Predicates = [HasStdExtCOrZca, HasRVCHints], hasSideEffects = 0, mayLoad = 0,
- mayStore = 0 in
-{
+ mayStore = 0 in {
let rd = 0 in
def C_NOP_HINT : RVInst16CI<0b000, 0b01, (outs), (ins simm6nonzero:$imm),
@@ -659,8 +657,7 @@ def C_LUI_HINT : RVInst16CI<0b011, 0b01, (outs GPRX0:$rd),
}
def C_MV_HINT : RVInst16CR<0b1000, 0b10, (outs GPRX0:$rs1), (ins GPRNoX0:$rs2),
- "c.mv", "$rs1, $rs2">, Sched<[WriteIALU, ReadIALU]>
-{
+ "c.mv", "$rs1, $rs2">, Sched<[WriteIALU, ReadIALU]> {
let Inst{11-7} = 0;
let DecoderMethod = "decodeRVCInstrRdRs2";
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 009c8380997aa..3d65a93e80170 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -258,8 +258,7 @@ class SegRegClass<LMULInfo m, int nf> {
//===----------------------------------------------------------------------===//
class VTypeInfo<ValueType Vec, ValueType Mas, int Sew, VReg Reg, LMULInfo M,
- ValueType Scal = XLenVT, RegisterClass ScalarReg = GPR>
-{
+ ValueType Scal = XLenVT, RegisterClass ScalarReg = GPR> {
ValueType Vector = Vec;
ValueType Mask = Mas;
int SEW = Sew;
@@ -281,8 +280,7 @@ class VTypeInfo<ValueType Vec, ValueType Mas, int Sew, VReg Reg, LMULInfo M,
class GroupVTypeInfo<ValueType Vec, ValueType VecM1, ValueType Mas, int Sew,
VReg Reg, LMULInfo M, ValueType Scal = XLenVT,
RegisterClass ScalarReg = GPR>
- : VTypeInfo<Vec, Mas, Sew, Reg, M, Scal, ScalarReg>
-{
+ : VTypeInfo<Vec, Mas, Sew, Reg, M, Scal, ScalarReg> {
ValueType VectorM1 = VecM1;
}
@@ -360,8 +358,7 @@ defset list<VTypeInfo> AllVectors = {
// This functor is used to obtain the int vector type that has the same SEW and
// multiplier as the input parameter type
-class GetIntVTypeInfo<VTypeInfo vti>
-{
+class GetIntVTypeInfo<VTypeInfo vti> {
// Equivalent integer vector type. Eg.
// VI8M1 → VI8M1 (identity)
// VF64M4 → VI64M4
@@ -394,14 +391,12 @@ defset list<MTypeInfo> AllMasks = {
def : MTypeInfo<vbool1_t, V_M8, "B64">;
}
-class VTypeInfoToWide<VTypeInfo vti, VTypeInfo wti>
-{
+class VTypeInfoToWide<VTypeInfo vti, VTypeInfo wti> {
VTypeInfo Vti = vti;
VTypeInfo Wti = wti;
}
-class VTypeInfoToFraction<VTypeInfo vti, VTypeInfo fti>
-{
+class VTypeInfoToFraction<VTypeInfo vti, VTypeInfo fti> {
VTypeInfo Vti = vti;
VTypeInfo Fti = fti;
}
@@ -499,11 +494,7 @@ defset list<VTypeInfoToWide> AllWidenableIntToFloatVectors = {
// This class holds the record of the RISCVVPseudoTable below.
// This represents the information we need in codegen for each pseudo.
// The definition should be consistent with `struct PseudoInfo` in
-// RISCVBaseInfo.h.
-class CONST8b<bits<8> val> {
- bits<8> V = val;
-}
-def InvalidIndex : CONST8b<0x80>;
+// RISCVInstrInfo.h.
class RISCVVPseudo {
Pseudo Pseudo = !cast<Pseudo>(NAME); // Used as a key.
Instruction BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
@@ -1862,8 +1853,7 @@ multiclass VPseudoIStore<bit Ordered> {
}
multiclass VPseudoVPOP_M {
- foreach mti = AllMasks in
- {
+ foreach mti = AllMasks in {
defvar mx = mti.LMul.MX;
defvar WriteVMPopV_MX = !cast<SchedWrite>("WriteVMPopV_" # mx);
defvar ReadVMPopV_MX = !cast<SchedRead>("ReadVMPopV_" # mx);
@@ -1877,8 +1867,7 @@ multiclass VPseudoVPOP_M {
}
multiclass VPseudoV1ST_M {
- foreach mti = AllMasks in
- {
+ foreach mti = AllMasks in {
defvar mx = mti.LMul.MX;
defvar WriteVMFFSV_MX = !cast<SchedWrite>("WriteVMFFSV_" # mx);
defvar ReadVMFFSV_MX = !cast<SchedRead>("ReadVMFFSV_" # mx);
@@ -1893,8 +1882,7 @@ multiclass VPseudoV1ST_M {
multiclass VPseudoVSFS_M {
defvar constraint = "@earlyclobber $rd";
- foreach mti = AllMasks in
- {
+ foreach mti = AllMasks in {
defvar mx = mti.LMul.MX;
defvar WriteVMSFSV_MX = !cast<SchedWrite>("WriteVMSFSV_" # mx);
defvar ReadVMSFSV_MX = !cast<SchedRead>("ReadVMSFSV_" # mx);
@@ -2400,8 +2388,7 @@ multiclass VPseudoVRCP_V {
multiclass PseudoVEXT_VF2 {
defvar constraints = "@earlyclobber $rd";
- foreach m = MxListVF2 in
- {
+ foreach m = MxListVF2 in {
defvar mx = m.MX;
defvar WriteVExtV_MX = !cast<SchedWrite>("WriteVExtV_" # mx);
defvar ReadVExtV_MX = !cast<SchedRead>("ReadVExtV_" # mx);
@@ -2419,8 +2406,7 @@ multiclass PseudoVEXT_VF2 {
multiclass PseudoVEXT_VF4 {
defvar constraints = "@earlyclobber $rd";
- foreach m = MxListVF4 in
- {
+ foreach m = MxListVF4 in {
defvar mx = m.MX;
defvar WriteVExtV_MX = !cast<SchedWrite>("WriteVExtV_" # mx);
defvar ReadVExtV_MX = !cast<SchedRead>("ReadVExtV_" # mx);
@@ -2438,8 +2424,7 @@ multiclass PseudoVEXT_VF4 {
multiclass PseudoVEXT_VF8 {
defvar constraints = "@earlyclobber $rd";
- foreach m = MxListVF8 in
- {
+ foreach m = MxListVF8 in {
defvar mx = m.MX;
defvar WriteVExtV_MX = !cast<SchedWrite>("WriteVExtV_" # mx);
defvar ReadVExtV_MX = !cast<SchedRead>("ReadVExtV_" # mx);
@@ -4394,8 +4379,7 @@ class VPatTernaryMaskTA<string intrinsic,
GPR:$vl, log2sew, TAIL_AGNOSTIC)>;
multiclass VPatUnaryS_M<string intrinsic_name,
- string inst>
-{
+ string inst> {
foreach mti = AllMasks in {
def : Pat<(XLenVT (!cast<Intrinsic>(intrinsic_name)
(mti.Mask VR:$rs1), VLOpFrag)),
@@ -4419,16 +4403,14 @@ multiclass VPatUnaryV_V_AnyMask<string intrinsic, string instruction,
}
multiclass VPatUnaryM_M<string intrinsic,
- string inst>
-{
+ string inst> {
foreach mti = AllMasks in {
def : VPatMaskUnaryNoMask<intrinsic, inst, mti>;
def : VPatMaskUnaryMask<intrinsic, inst, mti>;
}
}
-multiclass VPatUnaryV_M<string intrinsic, string instruction>
-{
+multiclass VPatUnaryV_M<string intrinsic, string instruction> {
foreach vti = AllIntegerVectors in {
let Predicates = GetVTypePredicates<vti>.Predicates in {
def : VPatUnaryNoMask<intrinsic, instruction, "M", vti.Vector, vti.Mask,
@@ -4440,10 +4422,8 @@ multiclass VPatUnaryV_M<string intrinsic, string instruction>
}
multiclass VPatUnaryV_VF<string intrinsic, string instruction, string suffix,
- list<VTypeInfoToFraction> fractionList>
-{
- foreach vtiTofti = fractionList in
- {
+ list<VTypeInfoToFraction> fractionList> {
+ foreach vtiTofti = fractionList in {
defvar vti = vtiTofti.Vti;
defvar fti = vtiTofti.Fti;
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
@@ -4472,8 +4452,7 @@ multiclass VPatUnaryV_V<string intrinsic, string instruction,
}
}
-multiclass VPatNullaryV<string intrinsic, string instruction>
-{
+multiclass VPatNullaryV<string intrinsic, string instruction> {
foreach vti = AllIntegerVectors in {
let Predicates = GetVTypePredicates<vti>.Predicates in {
def : Pat<(vti.Vector (!cast<Intrinsic>(intrinsic)
@@ -4508,8 +4487,7 @@ multiclass VPatBinaryM<string intrinsic,
int sew,
VReg result_reg_class,
VReg op1_reg_class,
- DAGOperand op2_kind>
-{
+ DAGOperand op2_kind> {
def : VPatBinaryM<intrinsic, inst, result_type, op1_type, op2_type,
sew, op1_reg_class, op2_kind>;
def : VPatBinaryMask<intrinsic, inst, result_type, op1_type, op2_type,
@@ -4526,8 +4504,7 @@ multiclass VPatBinary<string intrinsic,
int sew,
VReg result_reg_class,
VReg op1_reg_class,
- DAGOperand op2_kind>
-{
+ DAGOperand op2_kind> {
def : VPatBinaryNoMask<intrinsic, inst, result_type, op1_type, op2_type,
sew, op1_reg_class, op2_kind>;
def : VPatBinaryNoMaskTU<intrinsic, inst, result_type, op1_type, op2_type,
@@ -4546,8 +4523,7 @@ multiclass VPatBinaryRoundingMode<string intrinsic,
int sew,
VReg result_reg_class,
VReg op1_reg_class,
- DAGOperand op2_kind>
-{
+ DAGOperand op2_kind> {
def : VPatBinaryNoMaskRoundingMode<intrinsic, inst, result_type, op1_type, op2_type,
sew, op1_reg_class, op2_kind>;
def : VPatBinaryNoMaskTURoundingMode<intrinsic, inst, result_type, op1_type, op2_type,
@@ -4566,8 +4542,7 @@ multiclass VPatBinarySwapped<string intrinsic,
int sew,
VReg result_reg_class,
VReg op1_reg_class,
- DAGOperand op2_kind>
-{
+ DAGOperand op2_kind> {
def : VPatBinaryNoMaskSwapped<intrinsic, inst, result_type, op1_type, op2_type,
sew, op1_reg_class, op2_kind>;
def : VPatBinaryMaskSwapped<intrinsic, inst, result_type, op1_type, op2_type,
@@ -4586,8 +4561,7 @@ multiclass VPatBinaryCarryInTAIL<string intrinsic,
LMULInfo vlmul,
VReg result_reg_class,
VReg op1_reg_class,
- DAGOperand op2_kind>
-{
+ DAGOperand op2_kind> {
def : Pat<(result_type (!cast<Intrinsic>(intrinsic)
(result_type undef),
(op1_type op1_reg_class:$rs1),
@@ -4621,8 +4595,7 @@ multiclass VPatBinaryCarryIn<string intrinsic,
int sew,
LMULInfo vlmul,
VReg op1_reg_class,
- DAGOperand op2_kind>
-{
+ DAGOperand op2_kind> {
def : Pat<(result_type (!cast<Intrinsic>(intrinsic)
(op1_type op1_reg_class:$rs1),
(op2_type op2_kind:$rs2),
@@ -4643,8 +4616,7 @@ multiclass VPatBinaryMaskOut<string intrinsic,
int sew,
LMULInfo vlmul,
VReg op1_reg_class,
- DAGOperand op2_kind>
-{
+ DAGOperand op2_kind> {
def : Pat<(result_type (!cast<Intrinsic>(intrinsic)
(op1_type op1_reg_class:$rs1),
(op2_type op2_kind:$rs2),
@@ -4664,8 +4636,7 @@ multiclass VPatConversionTA<string intrinsic,
int sew,
LMULInfo vlmul,
VReg result_reg_class,
- VReg op1_reg_class>
-{
+ VReg op1_reg_class> {
def : VPatUnaryNoMask<intrinsic, inst, kind, result_type, op1_type,
sew, vlmul, result_reg_class, op1_reg_class>;
def : VPatUnaryMask<intrinsic, inst, kind, result_type, op1_type,
@@ -5366,8 +5337,7 @@ multiclass VPatBinaryV_VV_VX_VI_INT<string intrinsic, string instruction,
VPatBinaryV_VI<intrinsic#"_vx", instruction, vtilist, ImmType>;
multiclass VPatReductionV_VS<string intrinsic, string instruction, bit IsFloat = 0> {
- foreach vti = !if(IsFloat, NoGroupFloatVectors, NoGroupIntegerVectors) in
- {
+ foreach vti = !if(IsFloat, NoGroupFloatVectors, NoGroupIntegerVectors) in {
defvar vectorM1 = !cast<VTypeInfo>(!if(IsFloat, "VF", "VI") # vti.SEW # "M1");
let Predicates = GetVTypePredicates<vti>.Predicates in
defm : VPatTernaryTA<intrinsic, instruction, "VS",
@@ -5376,8 +5346,7 @@ multiclass VPatReductionV_VS<string intrinsic, string instruction, bit IsFloat =
vti.Log2SEW, vti.LMul,
VR, vti.RegClass, VR>;
}
- foreach gvti = !if(IsFloat, GroupFloatVectors, GroupIntegerVectors) in
- {
+ foreach gvti = !if(IsFloat, GroupFloatVectors, GroupIntegerVectors) in {
let Predicates = GetVTypePredicates<gvti>.Predicates in
defm : VPatTernaryTA<intrinsic, instruction, "VS",
gvti.VectorM1, gvti.Vector,
@@ -5388,8 +5357,7 @@ multiclass VPatReductionV_VS<string intrinsic, string instruction, bit IsFloat =
}
multiclass VPatReductionW_VS<string intrinsic, string instruction, bit IsFloat = 0> {
- foreach vti = !if(IsFloat, AllFloatVectors, AllIntegerVectors) in
- {
+ foreach vti = !if(IsFloat, AllFloatVectors, AllIntegerVectors) in {
defvar wtiSEW = !mul(vti.SEW, 2);
if !le(wtiSEW, 64) then {
defvar wtiM1 = !cast<VTypeInfo>(!if(IsFloat, "VF", "VI") # wtiSEW # "M1");
@@ -5405,10 +5373,8 @@ multiclass VPatReductionW_VS<string intrinsic, string instruction, bit IsFloat =
}
multiclass VPatConversionVI_VF<string intrinsic,
- string instruction>
-{
- foreach fvti = AllFloatVectors in
- {
+ string instruction> {
+ foreach fvti = AllFloatVectors in {
defvar ivti = GetIntVTypeInfo<fvti>.Vti;
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
GetVTypePredicates<ivti>.Predicates) in
@@ -5419,10 +5385,8 @@ multiclass VPatConversionVI_VF<string intrinsic,
}
multiclass VPatConversionVF_VI<string intrinsic,
- string instruction>
-{
- foreach fvti = AllFloatVectors in
- {
+ string instruction> {
+ foreach fvti = AllFloatVectors in {
defvar ivti = GetIntVTypeInfo<fvti>.Vti;
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
GetVTypePredicates<ivti>.Predicates) in
@@ -5433,8 +5397,7 @@ multiclass VPatConversionVF_VI<string intrinsic,
}
multiclass VPatConversionWI_VF<string intrinsic, string instruction> {
- foreach fvtiToFWti = AllWidenableFloatVectors in
- {
+ foreach fvtiToFWti = AllWidenableFloatVectors in {
defvar fvti = fvtiToFWti.Vti;
defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
@@ -5446,8 +5409,7 @@ multiclass VPatConversionWI_VF<string intrinsic, string instruction> {
}
multiclass VPatConversionWF_VI<string intrinsic, string instruction> {
- foreach vtiToWti = AllWidenableIntToFloatVectors in
- {
+ foreach vtiToWti = AllWidenableIntToFloatVectors in {
defvar vti = vtiToWti.Vti;
defvar fwti = vtiToWti.Wti;
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
@@ -5459,8 +5421,7 @@ multiclass VPatConversionWF_VI<string intrinsic, string instruction> {
}
multiclass VPatConversionWF_VF <string intrinsic, string instruction> {
- foreach fvtiToFWti = AllWidenableFloatVectors in
- {
+ foreach fvtiToFWti = AllWidenableFloatVectors in {
defvar fvti = fvtiToFWti.Vti;
defvar fwti = fvtiToFWti.Wti;
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
@@ -5472,8 +5433,7 @@ multiclass VPatConversionWF_VF <string intrinsic, string instruction> {
}
multiclass VPatConversionVI_WF <string intrinsic, string instruction> {
- foreach vtiToWti = AllWidenableIntToFloatVectors in
- {
+ foreach vtiToWti = AllWidenableIntToFloatVectors in {
defvar vti = vtiToWti.Vti;
defvar fwti = vtiToWti.Wti;
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
@@ -5485,8 +5445,7 @@ multiclass VPatConversionVI_WF <string intrinsic, string instruction> {
}
multiclass VPatConversionVF_WI <string intrinsic, string instruction> {
- foreach fvtiToFWti = AllWidenableFloatVectors in
- {
+ foreach fvtiToFWti = AllWidenableFloatVectors in {
defvar fvti = fvtiToFWti.Vti;
defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
@@ -5498,8 +5457,7 @@ multiclass VPatConversionVF_WI <string intrinsic, string instruction> {
}
multiclass VPatConversionVF_WF <string intrinsic, string instruction> {
- foreach fvtiToFWti = AllWidenableFloatVectors in
- {
+ foreach fvtiToFWti = AllWidenableFloatVectors in {
defvar fvti = fvtiToFWti.Vti;
defvar fwti = fvtiToFWti.Wti;
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index bb77e019ce364..e3aac7c788a22 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -29,8 +29,7 @@ multiclass VPatUSLoadStoreSDNode<ValueType type,
LMULInfo vlmul,
OutPatFrag avl,
VReg reg_class,
- int sew = !shl(1, log2sew)>
-{
+ int sew = !shl(1, log2sew)> {
defvar load_instr = !cast<Instruction>("PseudoVLE"#sew#"_V_"#vlmul.MX);
defvar store_instr = !cast<Instruction>("PseudoVSE"#sew#"_V_"#vlmul.MX);
// Load
@@ -45,8 +44,7 @@ multiclass VPatUSLoadStoreWholeVRSDNode<ValueType type,
int log2sew,
LMULInfo vlmul,
VReg reg_class,
- int sew = !shl(1, log2sew)>
-{
+ int sew = !shl(1, log2sew)> {
defvar load_instr =
!cast<Instruction>("VL"#!substr(vlmul.MX, 1)#"RE"#sew#"_V");
defvar store_instr =
@@ -60,8 +58,7 @@ multiclass VPatUSLoadStoreWholeVRSDNode<ValueType type,
(store_instr reg_class:$rs2, GPR:$rs1)>;
}
-multiclass VPatUSLoadStoreMaskSDNode<MTypeInfo m>
-{
+multiclass VPatUSLoadStoreMaskSDNode<MTypeInfo m> {
defvar load_instr = !cast<Instruction>("PseudoVLM_V_"#m.BX);
defvar store_instr = !cast<Instruction>("PseudoVSM_V_"#m.BX);
// Load
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