[PATCH] D154124: [WebAssembly] Fix incorrect assertion in SIMD reduction codegen

[Thomas Lively via Phabricator via llvm-commits]

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The codegen routine introduced in 18077e9fd688 <https://reviews.llvm.org/rG18077e9fd688443ca111111541e7e3a71236efd5> did not account for vectors with
more than 16 lanes. Remove the incorrect assertion and bail out of the
optimization when encountering this case. Add test cases that previously
triggered the assertion. Unfortunately, these test cases now have terrible
codegen, but that is at least better than crashing.

Fixes #63500.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D154124

Files:
  llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
  llvm/test/CodeGen/WebAssembly/simd-vecreduce-bool.ll

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