[llvm] d95c2c2 - [X86] Add tests for PR63475 (NFC)

[Nikita Popov via llvm-commits]

Author: Nikita Popov
Date: 2023-06-29T15:31:45+02:00
New Revision: d95c2c27f890bad94cdf9db6416e5a666527f0dd

URL: https://github.com/llvm/llvm-project/commit/d95c2c27f890bad94cdf9db6416e5a666527f0dd
DIFF: https://github.com/llvm/llvm-project/commit/d95c2c27f890bad94cdf9db6416e5a666527f0dd.diff

LOG: [X86] Add tests for PR63475 (NFC)

Added: 
    llvm/test/CodeGen/X86/pr63475.ll

Modified: 
    

Removed: 
    


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diff  --git a/llvm/test/CodeGen/X86/pr63475.ll b/llvm/test/CodeGen/X86/pr63475.ll
new file mode 100644
index 0000000000000..621e3f8624d7c
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr63475.ll
@@ -0,0 +1,92 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --no_x86_scrub_sp --version 2
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
+
+define void @caller() nounwind {
+; CHECK-LABEL: caller:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pushq %rax
+; CHECK-NEXT:    subq $8, %rsp
+; CHECK-NEXT:    xorl %edi, %edi
+; CHECK-NEXT:    xorl %esi, %esi
+; CHECK-NEXT:    xorl %edx, %edx
+; CHECK-NEXT:    xorl %ecx, %ecx
+; CHECK-NEXT:    xorl %r8d, %r8d
+; CHECK-NEXT:    xorl %r9d, %r9d
+; CHECK-NEXT:    pushq $42
+; CHECK-NEXT:    pushq $42
+; CHECK-NEXT:    pushq $42
+; CHECK-NEXT:    pushq $42
+; CHECK-NEXT:    pushq $42
+; CHECK-NEXT:    pushq $42
+; CHECK-NEXT:    pushq $42
+; CHECK-NEXT:    callq callee at PLT
+; CHECK-NEXT:    addq $64, %rsp
+; CHECK-NEXT:    popq %rax
+; CHECK-NEXT:    retq
+  call void @callee(ptr null, ptr null, ptr null, ptr null, ptr null, ptr null, <7 x i32> <i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42>)
+  ret void
+}
+
+; FIXME: This is a miscompile.
+define void @callee(ptr %p0, ptr %p1, ptr %p2, ptr %p3, ptr %p4, ptr %p5, <7 x i32> %arg) nounwind {
+; CHECK-LABEL: callee:
+; CHECK:       # %bb.0: # %start
+; CHECK-NEXT:    pushq %rbp
+; CHECK-NEXT:    pushq %r15
+; CHECK-NEXT:    pushq %r14
+; CHECK-NEXT:    pushq %r13
+; CHECK-NEXT:    pushq %r12
+; CHECK-NEXT:    pushq %rbx
+; CHECK-NEXT:    pushq %rax
+; CHECK-NEXT:    movl 112(%rsp), %ebx
+; CHECK-NEXT:    movl 104(%rsp), %ebp
+; CHECK-NEXT:    movl 96(%rsp), %r14d
+; CHECK-NEXT:    movl 76(%rsp), %r15d
+; CHECK-NEXT:    movl 72(%rsp), %r12d
+; CHECK-NEXT:    movl 64(%rsp), %edi
+; CHECK-NEXT:    movl 68(%rsp), %r13d
+; CHECK-NEXT:    callq use at PLT
+; CHECK-NEXT:    movl %r13d, %edi
+; CHECK-NEXT:    callq use at PLT
+; CHECK-NEXT:    movl %r12d, %edi
+; CHECK-NEXT:    callq use at PLT
+; CHECK-NEXT:    movl %r15d, %edi
+; CHECK-NEXT:    callq use at PLT
+; CHECK-NEXT:    movl %r14d, %edi
+; CHECK-NEXT:    callq use at PLT
+; CHECK-NEXT:    movl %ebp, %edi
+; CHECK-NEXT:    callq use at PLT
+; CHECK-NEXT:    movl %ebx, %edi
+; CHECK-NEXT:    callq use at PLT
+; CHECK-NEXT:    callq use at PLT
+; CHECK-NEXT:    addq $8, %rsp
+; CHECK-NEXT:    popq %rbx
+; CHECK-NEXT:    popq %r12
+; CHECK-NEXT:    popq %r13
+; CHECK-NEXT:    popq %r14
+; CHECK-NEXT:    popq %r15
+; CHECK-NEXT:    popq %rbp
+; CHECK-NEXT:    retq
+start:
+  %alloca = alloca [7 x i32], align 4
+  store <7 x i32> %arg, ptr %alloca, align 4
+  %extract0 = extractelement <7 x i32> %arg, i64 0
+  call void @use(i32 %extract0)
+  %extract1 = extractelement <7 x i32> %arg, i64 1
+  call void @use(i32 %extract1)
+  %extract2 = extractelement <7 x i32> %arg, i64 2
+  call void @use(i32 %extract2)
+  %extract3 = extractelement <7 x i32> %arg, i64 3
+  call void @use(i32 %extract3)
+  %extract4 = extractelement <7 x i32> %arg, i64 4
+  call void @use(i32 %extract4)
+  %extract5 = extractelement <7 x i32> %arg, i64 5
+  call void @use(i32 %extract5)
+  %extract6 = extractelement <7 x i32> %arg, i64 6
+  call void @use(i32 %extract6)
+  %extract7 = extractelement <7 x i32> %arg, i64 7
+  call void @use(i32 %extract7)
+  ret void
+}
+
+declare void @use(i32)