[PATCH] D154063: [AArch64] Handle 64bit vector s/umull from extracts

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: jaykang10, bipmis, labrinea, chill.
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This is similar to D153632 <https://reviews.llvm.org/D153632>, but for mul nodes instead of add/sub. They get recognised in LowerMUL in order to detect the `mul(ext, ext)`, in a way that will work for i64 nodes as well as i16/i32. This extends it to look for `mul(subvector_extract(ext(x), 0), subvector_extract(ext(y), 0))`, generating a `subvector_extract(mull(x,y))` if it matches.


https://reviews.llvm.org/D154063

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/neon-extadd-extract.ll

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