[PATCH] D154049: [DAG][AArch64] Handle vector types when expanding sdiv/udiv into mulh

Dave Green via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Jun 29 01:40:03 PDT 2023


dmgreen created this revision.
dmgreen added reviewers: RKSimon, craig.topper, SjoerdMeijer, samtebbs.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: All.
dmgreen requested review of this revision.
Herald added a project: LLVM.

The aarch64 backend will benefit from expanding 64vector sdiv/udiv into mulh using shift(mul(ext, ext)), as the larger type size is legal and the mul(ext, ext) can efficiently use smull/umull instructions. This extends the existing code in GetMULHS to handle vector types.


https://reviews.llvm.org/D154049

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/AArch64/srem-vector-lkk.ll
  llvm/test/CodeGen/AArch64/urem-vector-lkk.ll

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