[PATCH] D151449: [RISCV] Add DAG combine for CTTZ/CTLZ in the case of input 0

[Djordje Todorovic via Phabricator via llvm-commits]

djtodoro marked 6 inline comments as done.
djtodoro added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:11449
+
+  if (CTZ.getOpcode() == ISD::TRUNCATE || CTZ.getOpcode() == ISD::ZERO_EXTEND)
+    CTZ = CTZ.getOperand(0);
----------------
craig.topper wrote:
> Do we need to guard against truncating to a type that can't represent the entire bitwidth. Or does that just workout because the AND we create would be all ones in that case?
Yeah, I'd say that the AND will work it out, and I guess it is ok to rely on that.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:11465
+
+  SDValue CTZZeroDef;
+  switch (CTZ.getOpcode()) {
----------------
craig.topper wrote:
> Do we need a new variable? Can we assign over CTZ for the _UNDEF cases?
Actually no, it does not improve readability. I will remove it.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151449/new/

https://reviews.llvm.org/D151449