[llvm] a09a19b - [RISCV] Update computeKnownBitsForTargetNode for FPCLASS.

[Jianjian GUAN via llvm-commits]

Author: Jianjian GUAN
Date: 2023-06-29T14:13:01+08:00
New Revision: a09a19be5848547d894c31b4ac5da9878af76643

URL: https://github.com/llvm/llvm-project/commit/a09a19be5848547d894c31b4ac5da9878af76643
DIFF: https://github.com/llvm/llvm-project/commit/a09a19be5848547d894c31b4ac5da9878af76643.diff

LOG: [RISCV] Update computeKnownBitsForTargetNode for FPCLASS.

The fclass instruction only set one of the low 10 bits.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D154040

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    llvm/test/CodeGen/RISCV/float-intrinsics.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index ef9e96b6cca4c..e394d81cd5dbe 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -13147,6 +13147,11 @@ void RISCVTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
       Known.One.setBit(Log2_32(MinVLenB));
     break;
   }
+  case RISCVISD::FPCLASS: {
+    // fclass will only set one of the low 10 bits.
+    Known.Zero.setBitsFrom(10);
+    break;
+  }
   case ISD::INTRINSIC_W_CHAIN:
   case ISD::INTRINSIC_WO_CHAIN: {
     unsigned IntNo =

diff  --git a/llvm/test/CodeGen/RISCV/float-intrinsics.ll b/llvm/test/CodeGen/RISCV/float-intrinsics.ll
index 06adc9dd26834..e7ec2fdaf93fa 100644
--- a/llvm/test/CodeGen/RISCV/float-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/float-intrinsics.ll
@@ -1755,29 +1755,25 @@ define i1 @isqnan_fpclass(float %x) {
 ; RV32IF-LABEL: isqnan_fpclass:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fclass.s a0, fa0
-; RV32IF-NEXT:    slli a0, a0, 22
-; RV32IF-NEXT:    srli a0, a0, 31
+; RV32IF-NEXT:    srli a0, a0, 9
 ; RV32IF-NEXT:    ret
 ;
 ; RV32IZFINX-LABEL: isqnan_fpclass:
 ; RV32IZFINX:       # %bb.0:
 ; RV32IZFINX-NEXT:    fclass.s a0, a0
-; RV32IZFINX-NEXT:    slli a0, a0, 22
-; RV32IZFINX-NEXT:    srli a0, a0, 31
+; RV32IZFINX-NEXT:    srli a0, a0, 9
 ; RV32IZFINX-NEXT:    ret
 ;
 ; RV64IF-LABEL: isqnan_fpclass:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fclass.s a0, fa0
-; RV64IF-NEXT:    slli a0, a0, 54
-; RV64IF-NEXT:    srli a0, a0, 63
+; RV64IF-NEXT:    srli a0, a0, 9
 ; RV64IF-NEXT:    ret
 ;
 ; RV64IZFINX-LABEL: isqnan_fpclass:
 ; RV64IZFINX:       # %bb.0:
 ; RV64IZFINX-NEXT:    fclass.s a0, a0
-; RV64IZFINX-NEXT:    slli a0, a0, 54
-; RV64IZFINX-NEXT:    srli a0, a0, 63
+; RV64IZFINX-NEXT:    srli a0, a0, 9
 ; RV64IZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: isqnan_fpclass: