[PATCH] D154040: [RISCV] Update computeKnownBitsForTargetNode for FPCLASS.

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan created this revision.
jacquesguan added reviewers: craig.topper, asb, luismarques, frasercrmck.
Herald added subscribers: jobnoorman, luke, VincentWu, foad, vkmr, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya, arichardson.
Herald added a project: All.
jacquesguan requested review of this revision.
Herald added subscribers: llvm-commits, wangpc, eopXD, MaskRay.
Herald added a project: LLVM.

The fclass instruction only set one of the low 10 bits.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D154040

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/float-intrinsics.ll


Index: llvm/test/CodeGen/RISCV/float-intrinsics.ll
===================================================================
--- llvm/test/CodeGen/RISCV/float-intrinsics.ll
+++ llvm/test/CodeGen/RISCV/float-intrinsics.ll
@@ -1755,29 +1755,25 @@
 ; RV32IF-LABEL: isqnan_fpclass:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fclass.s a0, fa0
-; RV32IF-NEXT:    slli a0, a0, 22
-; RV32IF-NEXT:    srli a0, a0, 31
+; RV32IF-NEXT:    srli a0, a0, 9
 ; RV32IF-NEXT:    ret
 ;
 ; RV32IZFINX-LABEL: isqnan_fpclass:
 ; RV32IZFINX:       # %bb.0:
 ; RV32IZFINX-NEXT:    fclass.s a0, a0
-; RV32IZFINX-NEXT:    slli a0, a0, 22
-; RV32IZFINX-NEXT:    srli a0, a0, 31
+; RV32IZFINX-NEXT:    srli a0, a0, 9
 ; RV32IZFINX-NEXT:    ret
 ;
 ; RV64IF-LABEL: isqnan_fpclass:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fclass.s a0, fa0
-; RV64IF-NEXT:    slli a0, a0, 54
-; RV64IF-NEXT:    srli a0, a0, 63
+; RV64IF-NEXT:    srli a0, a0, 9
 ; RV64IF-NEXT:    ret
 ;
 ; RV64IZFINX-LABEL: isqnan_fpclass:
 ; RV64IZFINX:       # %bb.0:
 ; RV64IZFINX-NEXT:    fclass.s a0, a0
-; RV64IZFINX-NEXT:    slli a0, a0, 54
-; RV64IZFINX-NEXT:    srli a0, a0, 63
+; RV64IZFINX-NEXT:    srli a0, a0, 9
 ; RV64IZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: isqnan_fpclass:
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -13147,6 +13147,11 @@
       Known.One.setBit(Log2_32(MinVLenB));
     break;
   }
+  case RISCVISD::FPCLASS: {
+    // fclass will only set one of the low 10 bits.
+    Known.Zero.setBitsFrom(10);
+    break;
+  }
   case ISD::INTRINSIC_W_CHAIN:
   case ISD::INTRINSIC_WO_CHAIN: {
     unsigned IntNo =


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D154040.535611.patch
Type: text/x-patch
Size: 1747 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230629/e7485859/attachment.bin>