[PATCH] D145211: Relax cross-section branches

[Daniel Hoekwater via Phabricator via llvm-commits]

dhoekwater marked 2 inline comments as done.
dhoekwater added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.cpp:271-273
+  // Get a scratch register. It's important to get a virtual register because
+  // the register scavenger doesn't work with empty blocks.
+  Register ScratchReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
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arsenm wrote:
> dhoekwater wrote:
> > arsenm wrote:
> > > I think it would be better to just fix the scavenger to tolerate empty blocks. 
> > Agreed, but I think this would best be done in a different patch. This same approach is used by [AMDGPU/SI](https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp#L2556), [RISCV](https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp#L1015), and [LoongArch](https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp#L389). 
> Ugh. Is this even true anymore with backwards scavenging?
Yeah, this is still true. The signature of the function is `Register scavengeRegisterBackwards(const TargetRegisterClass &RC, MachineBasicBlock::iterator To, bool RestoreAfter, int SPAdj, bool AllowSpill = true);`, and `To` must be an iterator to a valid instruction because `scavengeRegisterBackwards` uses `To->getParent()`. It seems like fixing that could be reasonable since `RegisterScavenger` already has a `MBB` member, but again I think that's best done in a separate patch.


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https://reviews.llvm.org/D145211